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Various HDL (Verilog) IP Cores
Created
2015-05-30
54 commits to master branch, last one 3 years ago
A FPGA core for a simple SDRAM controller.
Created
2019-11-21
9 commits to master branch, last one 4 years ago
SPD Reader & Writer with Software Write Protection capabilities supporting Arduino and SMBus
Created
2020-05-26
719 commits to master branch, last one 10 months ago