8 results found Sort:

unihd-cag
skillbridge unihd-cag
34
162
lgpl-3.0
10
A seamless python to Cadence Virtuoso Skill interface
asic skill python cadence hardware virtuoso skillbridge cadence-virtuoso design-automation
Created 2019-09-24
402 commits to master branch, last one about a month ago
arm-university
VLSI-Fundamentals-Education-Kit arm-university
40
162
unknown
4
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical impl...
arm vlsi synopsys-design cadence-virtuoso hardware-designs computer-engineering electrical-engineering devices-circuits-materials microprocessor-implementation
Created 2021-11-25
32 commits to main branch, last one 6 months ago
muhammadaldacher
Analog-Design-of-Asynchronous-SAR-ADC muhammadaldacher
18
115
unknown
4
This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) implemented in 45nm CMOS technology.
adc analog digital sar-adcs sar-logic comparator cadence-virtuoso strongarm-comparator
Created 2021-03-17
8 commits to main branch, last one 2 months ago
zslwyuan
Basic-SIMD-Processor-Verilog-Tutorial zslwyuan
31
106
gpl-3.0
6
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
alu cpu simd adder verilog processor multiplier verilog-project cadence-virtuoso processor-design instruction-set-architecture
Created 2018-10-31
10 commits to master branch, last one about a year ago
muhammadaldacher
Layout-Design-of-an-8x8-SRAM-array muhammadaldacher
9
55
unknown
1
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Nois...
cmos sram layout matlab memory cadence-virtuoso
Created 2019-03-27
4 commits to master branch, last one about a year ago
muhammadaldacher
Analog-Design-of-1.9-GHz-PLL-system muhammadaldacher
11
51
unknown
3
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
pll matlab veriloga analog-design cadence-virtuoso
Created 2019-07-30
13 commits to master branch, last one 11 months ago
akdimitri
RRAM_COMPILER akdimitri
11
48
gpl-3.0
7
This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of Dimitris Antoniadis (PG Taught Student) at Imperial College Lond...
ram rram reram skill access memory random cadence calibre spectre compiler virtuoso memristor resistive rram-array verification rram-compiler cadence-virtuoso memristive-devices
Created 2021-02-18
225 commits to main branch, last one about a year ago
ColsonZhang
VerilogA-Wave-Generator ColsonZhang
11
36
unknown
2
The codes are used to generate the VerilogA code which can be directly used in the spectre simulation .The generated VerilogA code's fuction is to generate the specific waveforms according to your set...
veriloga virtuoso simulation cadence-virtuoso waveform-generator
Created 2021-09-30
5 commits to main branch, last one 2 years ago