zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

Date Created 2018-10-31 (6 years ago)

Commits 10 (last one 2 years ago)

Stargazers 123 (0 this week)

Watchers 6 (0 this week)

Forks 33

License gpl-3.0

Ranking

RepositoryStats indexes 579,238 repositories, of these zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial is ranked #250,498 (57th percentile) for total stargazers, and #296,655 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #183/533.

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial is also tagged with popular topics, for these it's ranked: cpu (#154/284), verilog (#132/279)

Other Information

zslwyuan/Basic-SIMD-Processor-Verilog-Tutorial has Github issues enabled, there are 3 open issues and 0 closed issues.

All Topics

alu cpu simd adder verilog processor multiplier verilog-project cadence-virtuoso processor-design instruction-set-architecture

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2 commits on the default branch (master) since jan '22

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The only known language in this repository is Verilog

updated: 2024-11-05 @ 11:34am, id: 155564755 / R_kgDOCUW60w