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zslwyuan
Basic-SIMD-Processor-Verilog-Tutorial zslwyuan
31
106
gpl-3.0
6
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clo...
alu cpu simd adder verilog processor multiplier verilog-project cadence-virtuoso processor-design instruction-set-architecture
Created 2018-10-31
10 commits to master branch, last one about a year ago
antonblanchard
vlsiffra antonblanchard
9
102
apache-2.0
7
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
vlsi adder booth dadda verilog multiplier amaranth-hdl physical-design
Created 2022-05-29
30 commits to main branch, last one 8 months ago
suoglu
Fixed-Floating-Point-Adder-Multiplier suoglu
12
55
other
5
16-bit Adder Multiplier hardware on Digilent Basys 3
fpga adder vivado verilog binary16 hardware multiplier fixed-point floating-point
Created 2017-06-06
105 commits to master branch, last one 10 months ago