12 results found Sort:

clash-lang
clash-compiler clash-lang
154
1.4k
other
55
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga vhdl haskell verilog systemverilog hardware-description-language
Created 2013-07-04
6,050 commits to master branch, last one 19 days ago
drom
awesome-hdl drom
95
971
unknown
62
Hardware Description Languages
hdl vhdl awesome verilog awesome-list hacktoberfest hardware-description-language
Created 2017-04-12
165 commits to master branch, last one 6 months ago
JulianKemmerer
PipelineC JulianKemmerer
49
602
gpl-3.0
24
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
c hls fpga vhdl python hardware pipelines fpga-programming fpga-acceleration fpga-accelerators hardware-description high-level-synthesis open-source-hardware hardware-description-language
Created 2018-05-03
1,721 commits to master branch, last one 4 days ago
WangXuan95
BSV_Tutorial_cn WangXuan95
42
514
gpl-3.0
11
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bsv hdl fpga verilog bluespec bluespec-systemverilog hardware-description-language
Created 2022-02-20
19 commits to main branch, last one about a year ago
SystemRDL
systemrdl-compiler SystemRDL
67
236
mit
27
SystemRDL 2.0 language compiler front-end
csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language
Created 2018-03-11
549 commits to main branch, last one 6 months ago
cucapra
filament cucapra
9
161
mit
8
Fearless hardware design
fpga type-system hardware-accelerator hardware-description-language
Created 2021-08-11
609 commits to main branch, last one 9 days ago
mit-plv
kami mit-plv
24
142
mit
14
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
coq bluespec proof-assistant hardware-verification hardware-description-language
Created 2017-07-11
1,470 commits to rv32i branch, last one about a month ago
mit-plv
koika mit-plv
9
140
gpl-3.0
24
A core language for rule-based hardware design 🦑
coq semantics compilation formal-methods programming-languages hardware-description-language
Created 2020-03-27
1,298 commits to master branch, last one 2 years ago
SystemRDL
PeakRDL SystemRDL
24
105
gpl-3.0
13
Control and status register code generator toolchain
apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language
Created 2020-04-05
67 commits to main branch, last one about a year ago
asyncvlsi
act asyncvlsi
22
100
gpl-2.0
16
ACT hardware description language and core tools.
cad chp eda hdl prs vlsi dataflow language vlsi-cad production-rules asynchronous-vlsi circuit-simulator design-automation dataflow-programming asynchronous-circuits hardware-description-language communicating-hardware-processes
Created 2018-12-10
1,960 commits to master branch, last one 20 hours ago
pc2
sus-compiler pc2
4
70
gpl-3.0
7
A new Hardware Design Language that keeps you in the driver's seat
hdl fpga tree-sitter fpga-programming programming-language hardware-description-language
Created 2022-08-08
462 commits to master branch, last one 15 hours ago
mikeroyal
VHDL-Guide mikeroyal
8
51
unknown
6
VHDL Guide
fpga vhdl awesome verilog hardware awesome-list vhdl-modules vhdl-examples vhdl-elearning vhdl-coursework hardware-designs awesome-resources hardware-description-language
Created 2021-11-08
7 commits to main branch, last one 2 years ago