11 results found Sort:

clash-lang
clash-compiler clash-lang
147
1.4k
other
57
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga vhdl haskell verilog systemverilog hardware-description-language
Created 2013-07-04
5,984 commits to master branch, last one 2 days ago
drom
awesome-hdl drom
92
909
unknown
61
Hardware Description Languages
hdl vhdl awesome verilog awesome-list hacktoberfest hardware-description-language
Created 2017-04-12
165 commits to master branch, last one about a month ago
JulianKemmerer
PipelineC JulianKemmerer
45
564
gpl-3.0
24
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
c hls fpga vhdl python hardware pipelines fpga-programming fpga-acceleration fpga-accelerators hardware-description high-level-synthesis open-source-hardware hardware-description-language
Created 2018-05-03
1,593 commits to master branch, last one 13 hours ago
WangXuan95
BSV_Tutorial_cn WangXuan95
40
476
gpl-3.0
9
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bsv hdl fpga verilog bluespec bluespec-systemverilog hardware-description-language
Created 2022-02-20
19 commits to main branch, last one 9 months ago
SystemRDL
systemrdl-compiler SystemRDL
58
221
mit
25
SystemRDL 2.0 language compiler front-end
csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language
Created 2018-03-11
549 commits to main branch, last one about a month ago
mit-plv
kami mit-plv
24
141
mit
14
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
coq bluespec proof-assistant hardware-verification hardware-description-language
Created 2017-07-11
1,469 commits to rv32i branch, last one 4 months ago
mit-plv
koika mit-plv
9
135
gpl-3.0
24
A core language for rule-based hardware design 🦑
coq semantics compilation formal-methods programming-languages hardware-description-language
Created 2020-03-27
1,298 commits to master branch, last one 2 years ago
cucapra
filament cucapra
7
133
mit
7
Fearless hardware design
fpga type-system hardware-accelerator hardware-description-language
Created 2021-08-11
596 commits to main branch, last one about a month ago
asyncvlsi
act asyncvlsi
20
95
gpl-2.0
15
ACT hardware description language and core tools.
cad chp eda hdl prs vlsi dataflow language vlsi-cad production-rules asynchronous-vlsi circuit-simulator design-automation dataflow-programming asynchronous-circuits hardware-description-language communicating-hardware-processes
Created 2018-12-10
1,867 commits to master branch, last one 18 days ago
SystemRDL
PeakRDL SystemRDL
16
77
gpl-3.0
12
Control and status register code generator toolchain
apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language
Created 2020-04-05
67 commits to main branch, last one 7 months ago
mikeroyal
VHDL-Guide mikeroyal
4
42
unknown
5
VHDL Guide
fpga vhdl awesome verilog hardware awesome-list vhdl-modules vhdl-examples vhdl-elearning vhdl-coursework hardware-designs awesome-resources hardware-description-language
Created 2021-11-08
7 commits to main branch, last one 2 years ago