14 results found Sort:

Haskell to VHDL/Verilog/SystemVerilog compiler
Created 2013-07-04
6,074 commits to master branch, last one 18 hours ago
97
997
unknown
62
Hardware Description Languages
Created 2017-04-12
167 commits to master branch, last one 4 days ago
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Created 2018-05-03
1,772 commits to master branch, last one 5 days ago
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程,介绍了BSV的调度、FIFO数据流、多态等高级特性,展示了BSV相比于传统Verilog开发的优势。
Created 2022-02-20
19 commits to main branch, last one about a year ago
SystemRDL 2.0 language compiler front-end
Created 2018-03-11
583 commits to main branch, last one about a month ago
Fearless hardware design
Created 2021-08-11
618 commits to main branch, last one a day ago
12
147
gpl-3.0
24
A core language for rule-based hardware design 🦑
Created 2020-03-27
1,298 commits to master branch, last one 2 years ago
25
146
mit
14
A Platform for High-Level Parametric Hardware Specification and its Modular Verification
Created 2017-07-11
1,470 commits to rv32i branch, last one 4 months ago
26
112
gpl-3.0
12
Control and status register code generator toolchain
Created 2020-04-05
77 commits to main branch, last one about a month ago
26
106
gpl-2.0
16
ACT hardware description language and core tools.
Created 2018-12-10
2,004 commits to master branch, last one 2 days ago
5
73
gpl-3.0
9
A new Hardware Design Language that keeps you in the driver's seat
Created 2022-08-08
605 commits to master branch, last one 9 days ago
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
Created 2021-04-19
10 commits to main branch, last one 8 months ago
Design and documentation for a very simple 4-bit processor named NibbleBuddy and its assembler.
Created 2024-11-30
8 commits to main branch, last one 2 months ago