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registers.nvim tversteeg

22

589

gpl-3.0

4

📑 Neovim plugin to preview the contents of the registers

lua nvim neovim plugin registers

Created 2021-02-11

200 commits to main branch, last one 6 months ago

systemrdl-compiler SystemRDL

58

221

mit

25

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

549 commits to main branch, last one about a month ago

open-register-design-tool Juniper

67

183

apache-2.0

43

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

Created 2016-06-14

453 commits to master branch, last one 11 months ago

PeakRDL SystemRDL

16

77

gpl-3.0

12

Control and status register code generator toolchain

apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language

Created 2020-04-05

67 commits to main branch, last one 7 months ago

regbits thanks4opensource

3

57

gpl-3.0

4

C++ templates for type-safe bit manipulation

embedded registers type-safety microcontroller

Created 2019-03-25

15 commits to master branch, last one 3 years ago

PeakRDL-regblock SystemRDL

29

47

gpl-3.0

15

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

Created 2020-11-11

172 commits to main branch, last one about a month ago

PeakRDL-uvm SystemRDL

25

45

gpl-3.0

9

Generate UVM register model from compiled SystemRDL input

eda uvm asic fpga registers uvm-ral-model uvm-register-model

Created 2019-08-23

47 commits to main branch, last one 7 months ago

Arch HoShiMin

7

31

mit

7

A bunch of architectural headers for i386 and AMD64

gdt idt msr pte svm vmx x86 arch vt-x amd-v intel ring0 eflags layout registers interrupts segmentation global-descriptor-table

Created 2023-01-05

21 commits to main branch, last one 8 months ago