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70

249

mit

25

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

590 commits to main branch, last one 22 days ago

71

198

apache-2.0

43

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

Created 2016-06-14

460 commits to master branch, last one 5 months ago

44

60

gpl-3.0

16

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

Created 2020-11-11

196 commits to main branch, last one 23 days ago