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58

221

mit

25

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

549 commits to main branch, last one about a month ago

67

183

apache-2.0

43

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

Created 2016-06-14

453 commits to master branch, last one 11 months ago

16

77

gpl-3.0

12

Control and status register code generator toolchain

apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language

Created 2020-04-05

67 commits to main branch, last one 7 months ago

29

47

gpl-3.0

15

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

Created 2020-11-11

172 commits to main branch, last one about a month ago