Search Results - RepositoryStats

70

249

mit

25

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

590 commits to main branch, last one 16 days ago

71

198

apache-2.0

43

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

Created 2016-06-14

460 commits to master branch, last one 5 months ago

27

119

gpl-3.0

13

Control and status register code generator toolchain

apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language

Created 2020-04-05

82 commits to main branch, last one 12 days ago

44

60

gpl-3.0

16

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

Created 2020-11-11

196 commits to main branch, last one 16 days ago

18

50

gpl-3.0

12

Generate address space documentation HTML from compiled SystemRDL input

eda asic fpga html registers documentation design-automation systemrdl-compiler documentation-generator

Created 2018-10-08

177 commits to main branch, last one about a year ago