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69

241

mit

26

SystemRDL 2.0 language compiler front-end

csr eda asic fpga registers systemrdl design-automation systemrdl-compiler register-descriptions hardware-description-language register-description-language

Created 2018-03-11

573 commits to main branch, last one 2 days ago

70

194

apache-2.0

44

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

eda uvm asic fpga jspec registers systemrdl systemverilog systemrdl-compiler register-descriptions

Created 2016-06-14

460 commits to master branch, last one 2 months ago

25

108

gpl-3.0

12

Control and status register code generator toolchain

apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language

Created 2020-04-05

77 commits to main branch, last one 11 days ago

43

55

gpl-3.0

15

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

csr asic fpga registers systemrdl systemverilog systemverilog-hdl systemrdl-compiler

Created 2020-11-11

186 commits to main branch, last one 10 days ago