SystemRDL / PeakRDL

Control and status register code generator toolchain

Date Created 2020-04-05 (4 years ago)

Commits 67 (last one about a year ago)

Stargazers 99 (0 this week)

Watchers 13 (0 this week)

Forks 24

License gpl-3.0

Ranking

RepositoryStats indexes 579,555 repositories, of these SystemRDL/PeakRDL is ranked #290,509 (50th percentile) for total stargazers, and #165,293 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #53,621/115,123.

SystemRDL/PeakRDL is also tagged with popular topics, for these it's ranked: command-line-tool (#413/668), fpga (#250/475), verilog (#149/280), eda (#85/137)

Other Information

SystemRDL/PeakRDL has 1 open pull request on Github, 1 pull request has been merged over the lifetime of the repository.

Github issues are enabled, there are 9 open issues and 30 closed issues.

There have been 10 releases, the latest one was published on 2023-10-26 (about a year ago) with the name 1.1.0.

Homepage URL: http://peakrdl.readthedocs.io

All Topics

apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

65 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Python but there's also others...

updated: 2024-11-06 @ 02:19am, id: 253298685 / R_kgDODxkH_Q