5 results found Sort:

rggen
rggen rggen
44
298
mit
14
Code generation tool for control and status registers
apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions
Created 2019-04-10
377 commits to master branch, last one 17 days ago
openshift
ansible-service-broker openshift
84
228
apache-2.0
212
Ansible Service Broker
go apb broker docker golang ansible openshift ansibleapp servicebroker openservicebrokerapi ansible-playbook-bundles
Created 2017-01-18
927 commits to master branch, last one 4 years ago
lucky-wfw
ARM_AMBA_Design lucky-wfw
34
101
gpl-3.0
3
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
ahb apb arm axi amba verilog
Created 2020-10-26
45 commits to main branch, last one 3 years ago
SystemRDL
PeakRDL SystemRDL
16
77
gpl-3.0
12
Control and status register code generator toolchain
apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language
Created 2020-04-05
67 commits to main branch, last one 7 months ago
prajwalgekkouga
AHB-to-APB-Bridge prajwalgekkouga
10
43
unknown
1
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equiva...
ahb apb amba fpga digital verilog modelsim verilog-project
Created 2022-10-04
6 commits to main branch, last one about a year ago