9 results found Sort:

pulp-platform
axi pulp-platform
278
1.2k
other
40
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip
Created 2018-04-12
1,323 commits to master branch, last one 2 days ago
taichi-ishitani
tvip-axi taichi-ishitani
109
387
apache-2.0
15
AMBA AXI VIP
axi uvm vip amba axi4 amba-axi systemverilog
Created 2018-09-22
113 commits to master branch, last one 8 months ago
rggen
rggen rggen
46
374
mit
14
Code generation tool for control and status registers
apb axi csr eda ral rtl soc uvm amba asic fpga vhdl verilog wishbone-bus systemverilog uvm-ral-model wiki-documents uvm-register-model register-descriptions
Created 2019-04-10
391 commits to master branch, last one about a month ago
ZipCPU
sdspi ZipCPU
41
254
unknown
10
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sdio sd-card verilog wishbone verilator sd-interface wishbone-bus spi-interface verilog-components
Created 2016-09-21
273 commits to master branch, last one 2 months ago
taichi-ishitani
tnoc taichi-ishitani
46
171
apache-2.0
13
Network on Chip Implementation written in SytemVerilog
axi noc uvm amba axi4 amba-axi systemverilog network-on-chip
Created 2017-12-12
193 commits to master branch, last one 2 years ago
hdl-modules
hdl-modules hdl-modules
27
159
bsd-3-clause
6
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
ip amd axi cdc eda rtl asic fifo fpga vhdl intel altera efinix vivado xilinx axi-lite hardware microsemi asynchronous-fifo clock-domain-crossing
Created 2023-11-30
549 commits to main branch, last one 4 days ago
lucky-wfw
ARM_AMBA_Design lucky-wfw
34
119
gpl-3.0
3
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
ahb apb arm axi amba verilog
Created 2020-10-26
45 commits to main branch, last one 3 years ago
SystemRDL
PeakRDL SystemRDL
27
118
gpl-3.0
13
Control and status register code generator toolchain
apb axi csr eda uvm amba asic fpga verilog registers systemverilog command-line-tool systemrdl-compiler uvm-register-model register-descriptions hardware-description-language
Created 2020-04-05
82 commits to main branch, last one 11 days ago
hdl-registers
hdl-registers hdl-registers
7
58
bsd-3-clause
5
An open-source HDL register code generator fast enough to run in real time.
c axi csr eda rtl asic fpga html vhdl python axi-lite register cplusplus generator register-interface
Created 2023-11-29
573 commits to main branch, last one 9 days ago