13 results found Sort:

pulp-platform
axi pulp-platform
272
1.2k
other
39
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
ip axi rtl asic axi4 fpga hardware axi4-lite systemverilog network-on-chip
Created 2018-04-12
1,311 commits to master branch, last one 7 days ago
chipsalliance
Cores-VeeR-EH1 chipsalliance
221
831
apache-2.0
58
VeeR EH1 core
rtl axi4 fpga risc veer riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2019-06-02
125 commits to main branch, last one 2 years ago
Hanley-Yao
Zynq7010_eink_controller Hanley-Yao
45
371
mit
10
这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
axi4 eink fdma fpga zynq verilog controller
Created 2021-09-16
5 commits to master branch, last one about a year ago
taichi-ishitani
tvip-axi taichi-ishitani
106
366
apache-2.0
16
AMBA AXI VIP
axi uvm vip amba axi4 amba-axi systemverilog
Created 2018-09-22
113 commits to master branch, last one 6 months ago
chipsalliance
Cores-VeeR-EL2 chipsalliance
76
253
apache-2.0
29
VeeR EL2 Core
el2 rtl axi4 fpga riscv risc-v fusesoc riscv32 ahb-lite processor verilator asic-design western-digital open-source-hardware
Created 2020-01-09
769 commits to main branch, last one 5 hours ago
taichi-ishitani
tnoc taichi-ishitani
44
161
apache-2.0
13
Network on Chip Implementation written in SytemVerilog
axi noc uvm amba axi4 amba-axi systemverilog network-on-chip
Created 2017-12-12
193 commits to master branch, last one 2 years ago
WangXuan95
FPGA-DDR-SDRAM WangXuan95
34
154
gpl-3.0
4
An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
rtl axi4 ddr1 fpga verilog ddr-sdram soft-core controller
Created 2021-01-27
19 commits to main branch, last one about a year ago
aignacio
ravenoc aignacio
35
152
mit
6
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
noc axi4 flits mpsoc router network-on-chip virtual-channels
Created 2020-03-14
181 commits to master branch, last one about a month ago
OSVVM
AXI4 OSVVM
18
130
other
11
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
tlm vip axi4 vhdl osvvm axi4-lite testbench simulation axi4-stream verification simulation-modeling verification-component
Created 2018-03-17
659 commits to main branch, last one 18 days ago
loykylewong
FPGA-Application-Development-and-Simulation loykylewong
30
126
mit
5
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
cic dds dsp fft fir i2c i2s iir qam spi axi4 fpga uart adpll cordic verilog modelsim modulation systemverilog digital-signal-processing
Created 2019-05-31
26 commits to master branch, last one 2 months ago
dpretet
axi-crossbar dpretet
26
125
mit
3
An AXI4 crossbar implementation in SystemVerilog
arm soc amba asic axi4 fpga riscv riscv32 riscv64 verilog crossbar fpga-soc monodraw axi4-full axi4-lite processor asic-design interconnect axi4-protocol
Created 2021-09-23
57 commits to main branch, last one 29 days ago
ultraembedded
core_dbg_bridge ultraembedded
17
59
lgpl-2.1
5
UART -> AXI Bridge
axi4 fpga uart verilog
Created 2019-08-11
5 commits to master branch, last one 3 years ago
airhdl
spi-to-axi-bridge airhdl
11
45
apache-2.0
3
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
spi axi4 vhdl systemverilog
Created 2022-05-09
40 commits to main branch, last one 2 years ago