airhdl / spi-to-axi-bridge

An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

airhdl
airhdl
Date Created 2022-05-09 (2 years ago)
Commits 40 (last one 2 years ago)
Stargazers 49 (0 this week)
Watchers 3 (0 this week)
Forks 12
License apache-2.0
Ranking

RepositoryStats indexes 633,155 repositories, of these airhdl/spi-to-axi-bridge is ranked #498,258 (21st percentile) for total stargazers, and #418,158 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #158/201.

Other Information

airhdl/spi-to-axi-bridge has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 3 open issues and 0 closed issues.

All Topics
spi axi4 vhdl systemverilog

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

40 commits on the default branch (main) since jan '22

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Yearly Commits

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Issue History

Total Issues
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Closed Issues
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Languages

The primary language is VHDL but there's also others...

VHDLVHDLSystemVerilogSystemVerilogPrologProlog

updated: 2025-03-10 @ 04:50am, id: 490397575 / R_kgDOHTrfhw