Statistics for language VHDL

All in one vscode plugin for HDL development

Open Logic FPGA Standard Library

这个仓库存放了北京理工大学计科专业相关课程资料，欢迎Star & PR。

FPGA project

Second version of homemade 30 MHz - 6 GHz VNA

All in one vscode plugin for HDL development

Open Logic FPGA Standard Library

这个仓库存放了北京理工大学计科专业相关课程资料，欢迎Star & PR。

FPGA project

Second version of homemade 30 MHz - 6 GHz VNA

All in one vscode plugin for HDL development

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 2008/93/87 simulator

Open Logic FPGA Standard Library

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future...

General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。

All in one vscode plugin for HDL development

A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC

FPGA和USB3.0桥片实现USB3.0通信

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

All in one vscode plugin for HDL development

Open Logic FPGA Standard Library

VHDL 2008/93/87 simulator

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

All in one vscode plugin for HDL development

General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。

Zynq/FPGA实现CNN手写数字(0-9)识别

This is a repository for the LibreSDR using the Artix 7 FPGA and AD9361

ChisFlash is an open-source GBA🎮 flashcart that supports 1M of save type.

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

No description

Homeworks and projects suits for BJUTers major in CS

General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。

Open Logic FPGA Standard Library

All in one vscode plugin for HDL development

VHDL 2008/93/87 simulator

:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

No description

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...

Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt

A collection of reusable, high-quality, peer-reviewed VHDL building blocks.

这个仓库存放了北京理工大学计科专业相关课程资料，欢迎Star & PR。