chili-chips-ba / wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Date Created 2024-07-13 (8 months ago)
Commits 234 (last one a day ago)
Stargazers 73 (0 this week)
Watchers 10 (0 this week)
Forks 0
License bsd-3-clause
Ranking

RepositoryStats indexes 633,155 repositories, of these chili-chips-ba/wireguard-fpga is ranked #380,754 (40th percentile) for total stargazers, and #200,924 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #106/201.

chili-chips-ba/wireguard-fpga is also tagged with popular topics, for these it's ranked: embedded (#511/704),  vpn (#474/647),  fpga (#343/515),  verilog (#211/308),  wireguard (#204/292),  risc-v (#172/283)

Other Information

chili-chips-ba/wireguard-fpga has Github issues enabled, there are 14 open issues and 1 closed issue.

Homepage URL: https://nlnet.nl/project/KlusterLab-Wireguard

Star History

Github stargazers over time

8080707060605050404030302020101000Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Watcher History

Github watchers over time, collection started in '23

10109.59.5998.58.5887.57.577Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Recent Commit History

234 commits on the default branch (main) since jan '22

250250200200150150100100505000Aug '24Aug '24Sep '24Sep '24Oct '24Oct '24Nov '24Nov '24Dec '24Dec '2420252025Feb '25Feb '25Mar '25Mar '25

Yearly Commits

Commits to the default branch (main) per year

14014012012010010080806060404020200020242024

Issue History

Total Issues
Open Issues
Closed Issues
1616141412121010886644220015 Nov15 NovDec '24Dec '2415 Dec15 DecJan '25Jan '2515 Jan15 JanFeb '25Feb '2515 Feb15 FebMar '25Mar '2515 Mar15 Mar

Languages

The primary language is VHDL but there's also others...

VHDLVHDLVerilogVerilogSystemVerilogSystemVerilogVVCoqCoqOtherOtherC++C++ShellShellCCTclTclAssemblyAssembly

updated: 2025-03-29 @ 08:01am, id: 828348416 / R_kgDOMV-YAA