chili-chips-ba / wireguard-fpga

Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!

Date Created 2024-07-13 (2 months ago)

Commits 18 (last one 10 days ago)

Stargazers 26 (2 this week)

Watchers 7 (0 this week)

Forks 0

License bsd-3-clause

Ranking

RepositoryStats indexes 565,600 repositories, of these chili-chips-ba/wireguard-fpga is ranked #556,686 (2nd percentile) for total stargazers, and #265,501 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #167/170.

chili-chips-ba/wireguard-fpga is also tagged with popular topics, for these it's ranked: embedded (#627/632), vpn (#556/563), fpga (#460/462), verilog (#270/272), wireguard (#261/266), risc-v (#250/253)

Other Information

Homepage URL: https://nlnet.nl/project/KlusterLab-Wireguard

All Topics

iss rtl vpn fpga vproc cocotb risc-v verilog embedded verilator wireguard

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

18 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

No issues have been posted

Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-09-28 @ 01:32pm, id: 828348416 / R_kgDOMV-YAA