Trending repositories for language VHDL
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Develop an end-to-end hypothetical reference model, network architectures, precision time tools, performance objectives and the methods to distribute, operate, monitor time synchronization within data...
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improveme...
Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
Official firmware under devolpement for MSX++ computers and compatibles: 1chipMSX, Zemmix Neo (KR/BR), SX-1 (regular, Mini, Mini+), SM-X and SX-2.
ChisFlash is an open-source GBA🎮 flashcart that supports 1M of save type.
"Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
Official firmware under devolpement for MSX++ computers and compatibles: 1chipMSX, Zemmix Neo (KR/BR), SX-1 (regular, Mini, Mini+), SM-X and SX-2.
ChisFlash is an open-source GBA🎮 flashcart that supports 1M of save type.
"Mehmet Burak Aykenar" YouTube kanalında yayınlanan VHDL ve FPGA dersleri ile ilgili kodları içermektedir.
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Image Processing Toolbox in Verilog using Basys3 FPGA
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improveme...
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
Develop an end-to-end hypothetical reference model, network architectures, precision time tools, performance objectives and the methods to distribute, operate, monitor time synchronization within data...
ChisFlash is an open-source GBA🎮 flashcart that supports 1M of save type.
General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
Image Processing Toolbox in Verilog using Basys3 FPGA
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
ChisFlash is an open-source GBA🎮 flashcart that supports 1M of save type.
This is a repository for the LibreSDR using the Artix 7 FPGA and AD9361
Official firmware under devolpement for MSX++ computers and compatibles: 1chipMSX, Zemmix Neo (KR/BR), SX-1 (regular, Mini, Mini+), SM-X and SX-2.
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
RiscV based SOC with 2D and 3D graphics acceleration for Tang Nano 20K
a Real-time image recognition project with RTL accelerator and ZYNQ Architecture
Open source Zynq timestamping implementation from Software Radio Systems (SRS)
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
ChisFlash is an open-source GBA🎮 flashcart that supports 1M of save type.
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
Develop an end-to-end hypothetical reference model, network architectures, precision time tools, performance objectives and the methods to distribute, operate, monitor time synchronization within data...
A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future...
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
ChisFlash is an open-source GBA🎮 flashcart that supports 1M of save type.
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door...
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
a Real-time image recognition project with RTL accelerator and ZYNQ Architecture
Virtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments
Commodore C64 core for the Tang Nano 20K Primer 25K Mega 60k and Mega 138K Pro FPGA
Network Development Kit (NDK) for FPGA cards with example application
NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art HBM2 chips and DDR4 modules of different form factors. Six prototy...
