Trending repositories for language VHDL
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for SUSTech EE332-Digital-System-Designing.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Generating Airborne Ultrasonic Amplitude Patterns Using an Open Hardware Phased Array
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for SUSTech EE332-Digital-System-Designing.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Generating Airborne Ultrasonic Amplitude Patterns Using an Open Hardware Phased Array
OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
A hardware h264 video encoder written in VHDL. Designed to be synthesized into an FPGA. Initial testing is using Xilinx tools and FPGAs but it is not specific to Xilinx.
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improveme...
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improveme...
Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
Commodore C64 core for the Tang Nano 20K, Primer 25K and Mega 138K FPGA
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
OpenXenium - Open Source Xenium Modchip CPLD replacement project for the Original Xbox
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Commodore C64 core for the Tang Nano 20K, Primer 25K and Mega 138K FPGA
Code Repository for The FPGA Programming Handbook Second Edition, Published by Packt
A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
A pseudo Minecraft game running on Artix-7 FPGA in VHDL. Also the final project for SUSTech EE332-Digital-System-Designing.
NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Commodore C64 core for the Tang Nano 20K, Primer 25K and Mega 138K FPGA
a Real-time image recognition project with RTL accelerator and ZYNQ Architecture
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future...
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
NSCSCC2022龙芯杯个人赛，MIPS32，59MHz经典五级流水线架构，易于初学者阅读（计算机组成原理，自己动手写CPU）
DRAM Bender is the first open source DRAM testing infrastructure that can be used to easily and comprehensively test state-of-the-art DDR4 modules of different form factors. Five prototypes are availa...
You can find the documents, assignments and projects of some of the courses given in Electronics and Communication engineering at Istanbul Technical University here.
Documenting the Catapult v3 SmartNIC FPGA boards (Dragontails Peak & Longs Peak)
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
