UVVM / UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

UVVM
UVVM
Date Created 2016-01-21 (8 years ago)
Commits 3,001 (last one 15 days ago)
Stargazers 369 (0 this week)
Watchers 55 (0 this week)
Forks 94
License apache-2.0
Ranking

RepositoryStats indexes 579,555 repositories, of these UVVM/UVVM is ranked #112,886 (81st percentile) for total stargazers, and #37,001 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #15/176.

Other Information

UVVM/UVVM has 6 open pull requests on Github, 41 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 23 open issues and 174 closed issues.

Homepage URL: https://uvvm.github.io/

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

346 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is VHDL but there's also others...

updated: 2024-11-05 @ 03:37pm, id: 50093478 / R_kgDOAvxdpg