UVVM / UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

Date Created 2016-01-21 (8 years ago)

Commits 3,001 (last one 2 months ago)

Stargazers 380 (2 this week)

Watchers 55 (0 this week)

Forks 95

License apache-2.0

Ranking

RepositoryStats indexes 595,856 repositories, of these UVVM/UVVM is ranked #112,351 (81st percentile) for total stargazers, and #37,200 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #17/183.

Other Information

UVVM/UVVM has 10 open pull requests on Github, 41 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 25 open issues and 178 closed issues.

Homepage URL: https://uvvm.github.io/

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

346 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is VHDL but there's also others...

updated: 2024-12-21 @ 12:55pm, id: 50093478 / R_kgDOAvxdpg