UVVM / UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

UVVM
UVVM
Date Created 2016-01-21 (8 years ago)
Commits 513 (last one 3 hours ago)
Stargazers 341 (0 this week)
Watchers 54 (0 this week)
Forks 86
License apache-2.0
Ranking

RepositoryStats indexes 535,551 repositories, of these UVVM/UVVM is ranked #114,029 (79th percentile) for total stargazers, and #37,432 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #15/162.

Other Information

UVVM/UVVM has 3 open pull requests on Github, 38 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 28 open issues and 158 closed issues.

Homepage URL: https://uvvm.github.io/

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Recent Commit History

59 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is VHDL but there's also others...

updated: 2024-07-03 @ 01:12pm, id: 50093478 / R_kgDOAvxdpg