UVVM / UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

UVVM
UVVM
Date Created 2016-01-21 (9 years ago)
Commits 3,034 (last one 8 days ago)
Stargazers 394 (2 this week)
Watchers 53 (0 this week)
Forks 99
License apache-2.0
Ranking

RepositoryStats indexes 634,548 repositories, of these UVVM/UVVM is ranked #113,862 (82nd percentile) for total stargazers, and #38,617 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #18/201.

Other Information

UVVM/UVVM has 3 open pull requests on Github, 50 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 17 open issues and 186 closed issues.

Homepage URL: https://uvvm.github.io/

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

379 commits on the default branch (master) since jan '22

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Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
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Closed Issues
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Languages

The primary language is VHDL but there's also others...

VHDLVHDLPythonPythonStataStataShellShellMakefileMakefileHTMLHTML

updated: 2025-04-02 @ 02:38am, id: 50093478 / R_kgDOAvxdpg