jakubcabal / uart-for-fpga

Simple UART controller for FPGA written in VHDL

jakubcabal
jakubcabal
Date Created 2015-07-24 (9 years ago)
Commits 62 (last one 3 years ago)
Stargazers 95 (0 this week)
Watchers 10 (0 this week)
Forks 28
License mit
Ranking

RepositoryStats indexes 631,885 repositories, of these jakubcabal/uart-for-fpga is ranked #317,205 (50th percentile) for total stargazers, and #200,615 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #84/201.

jakubcabal/uart-for-fpga is also tagged with popular topics, for these it's ranked: simulation (#596/1069),  fpga (#280/516)

Other Information

jakubcabal/uart-for-fpga has Github issues enabled, there is 1 open issue and 2 closed issues.

There have been 4 releases, the latest one was published on 2021-04-10 (3 years ago) with the name Simple UART for FPGA v1.3.

Star History

Github stargazers over time

1001009090808070706060505040403030202010100020162016201720172018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

11111111111110.510.510101010101020232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

25252020151510105500201520152016201620172017201820182019201920202020202120212022202220242024

Issue History

Total Issues
Open Issues
Closed Issues
332.52.5221.51.5110.50.50020192019202020202021202120222022202320232024202420252025

Languages

The primary language is VHDL but there's also others...

VHDLVHDLTclTcl

updated: 2025-03-12 @ 08:14pm, id: 39646455 / R_kgDOAlz09w