jakubcabal / uart-for-fpga

Simple UART controller for FPGA written in VHDL

Date Created 2015-07-24 (9 years ago)
Commits 62 (last one 3 years ago)
Stargazers 93 (0 this week)
Watchers 11 (0 this week)
Forks 28
License mit
Ranking

RepositoryStats indexes 619,220 repositories, of these jakubcabal/uart-for-fpga is ranked #317,567 (49th percentile) for total stargazers, and #194,074 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #84/196.

jakubcabal/uart-for-fpga is also tagged with popular topics, for these it's ranked: simulation (#593/1048),  fpga (#276/503)

Other Information

jakubcabal/uart-for-fpga has Github issues enabled, there is 1 open issue and 2 closed issues.

There have been 4 releases, the latest one was published on 2021-04-10 (3 years ago) with the name Simple UART for FPGA v1.3.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is VHDL but there's also others...

VHDLVHDLTclTcl

updated: 2025-02-10 @ 12:40am, id: 39646455 / R_kgDOAlz09w