jakubcabal / uart-for-fpga

Simple UART controller for FPGA written in VHDL

Date Created 2015-07-24 (9 years ago)

Commits 62 (last one 3 years ago)

Stargazers 92 (0 this week)

Watchers 11 (0 this week)

Forks 27

License mit

Ranking

RepositoryStats indexes 595,856 repositories, of these jakubcabal/uart-for-fpga is ranked #311,344 (48th percentile) for total stargazers, and #192,427 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #79/183.

jakubcabal/uart-for-fpga is also tagged with popular topics, for these it's ranked: simulation (#582/1017), fpga (#274/488)

Other Information

jakubcabal/uart-for-fpga has Github issues enabled, there is 1 open issue and 2 closed issues.

There have been 4 releases, the latest one was published on 2021-04-10 (3 years ago) with the name Simple UART for FPGA v1.3.

All Topics

fpga ghdl uart vhdl cyc1000 wishbone controller simulation wishbone-bus uart-loopback uart-controller

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0 commits on the default branch (master) since jan '22

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The primary language is VHDL but there's also others...

updated: 2024-12-18 @ 11:15pm, id: 39646455 / R_kgDOAlz09w