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pConst
basic_verilog pConst
379
1.6k
unknown
60
Must-have verilog systemverilog modules
hls pwm tcl fifo fpga uart delay altera xilinx encoder uart-tx verilog debounce spi-master synchronizer uart-verilog spi-interface uart-protocol uart-receiver uart-controller
Created 2015-12-14
261 commits to master branch, last one 4 months ago
jakubcabal
uart-for-fpga jakubcabal
27
91
mit
11
Simple UART controller for FPGA written in VHDL
fpga ghdl uart vhdl cyc1000 wishbone controller simulation wishbone-bus uart-loopback uart-controller
Created 2015-07-24
62 commits to master branch, last one 3 years ago