pConst / basic_verilog

Must-have verilog systemverilog modules

pConst
pConst
Date Created 2015-12-14 (9 years ago)
Commits 262 (last one 4 months ago)
Stargazers 1,731 (3 this week)
Watchers 59 (0 this week)
Forks 394
License unknown
Ranking

RepositoryStats indexes 626,055 repositories, of these pConst/basic_verilog is ranked #31,156 (95th percentile) for total stargazers, and #34,014 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #9/610.

pConst/basic_verilog is also tagged with popular topics, for these it's ranked: fpga (#16/507),  verilog (#14/305),  hls (#43/259)

Star History

Github stargazers over time

1.8k1.8k1.6k1.6k1.4k1.4k1.2k1.2k1k1k80080060060040040020020000201720172018201820192019202020202021202120222022202320232024202420252025

Watcher History

Github watchers over time, collection started in '23

6060595958585757565655555454535320232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Recent Commit History

108 commits on the default branch (master) since jan '22

120120100100808060604040202000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
1111110.50.5000000Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogSystemVerilogSystemVerilogVHDLVHDLHTMLHTMLC++C++JavaJavaTclTclOtherOtherCCShellShellPascalPascal

updated: 2025-03-13 @ 12:01am, id: 47992542 / R_kgDOAtxO3g