pConst / basic_verilog

Must-have verilog systemverilog modules

pConst
pConst
Date Created 2015-12-14 (8 years ago)
Commits 261 (last one 4 months ago)
Stargazers 1,645 (1 this week)
Watchers 60 (0 this week)
Forks 379
License unknown
Ranking

RepositoryStats indexes 579,238 repositories, of these pConst/basic_verilog is ranked #31,301 (95th percentile) for total stargazers, and #33,407 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #8/533.

pConst/basic_verilog is also tagged with popular topics, for these it's ranked: fpga (#16/474),  verilog (#13/279),  hls (#45/250)

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

107 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-06 @ 10:28pm, id: 47992542 / R_kgDOAtxO3g