pConst / basic_verilog

Must-have verilog systemverilog modules

pConst
pConst
Date Created 2015-12-14 (8 years ago)
Commits 262 (last one 13 days ago)
Stargazers 1,657 (7 this week)
Watchers 60 (0 this week)
Forks 380
License unknown
Ranking

RepositoryStats indexes 584,353 repositories, of these pConst/basic_verilog is ranked #31,219 (95th percentile) for total stargazers, and #33,469 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #8/535.

pConst/basic_verilog is also tagged with popular topics, for these it's ranked: fpga (#16/478),  verilog (#13/282),  hls (#45/250)

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

108 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-20 @ 05:41pm, id: 47992542 / R_kgDOAtxO3g