pConst / basic_verilog

Must-have verilog systemverilog modules

pConst
pConst
Date Created 2015-12-14 (8 years ago)
Commits 257 (last one 2 days ago)
Stargazers 1,474 (2 this week)
Watchers 58 (0 this week)
Forks 341
License unknown
Ranking

RepositoryStats indexes 534,551 repositories, of these pConst/basic_verilog is ranked #33,504 (94th percentile) for total stargazers, and #34,427 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #8/459.

pConst/basic_verilog is also tagged with popular topics, for these it's ranked: fpga (#18/435),  verilog (#14/257),  hls (#45/231)

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

103 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-06-28 @ 07:31am, id: 47992542 / R_kgDOAtxO3g