3 results found Sort:
Must-have verilog systemverilog modules
Created
2015-12-14
262 commits to master branch, last one 15 days ago
A simple, basic, formally verified UART controller
Created
2016-09-21
160 commits to master branch, last one 9 months ago
A simple implementation of a UART modem in Verilog.
Created
2017-02-04
50 commits to master branch, last one 3 years ago