2 results found Sort:

pConst
basic_verilog pConst
380
1.7k
unknown
60
Must-have verilog systemverilog modules
hls pwm tcl fifo fpga uart delay altera xilinx encoder uart-tx verilog debounce spi-master synchronizer uart-verilog spi-interface uart-protocol uart-receiver uart-controller
Created 2015-12-14
262 commits to master branch, last one 13 days ago
PowerBroker2
pySerialTransfer PowerBroker2
35
147
mit
11
Python package to transfer data in a fast, reliable, and packetized form
uart python robust serial arduinos serialport uart-bridge transfer-data uart-protocol uart-interface serial-communication packet-capturing-libraries
Created 2019-11-29
190 commits to master branch, last one 7 months ago