17 results found Sort:
- Filter by Primary Language:
- VHDL (4)
- Verilog (3)
- Python (3)
- C (2)
- SystemVerilog (2)
- Scala (1)
- Makefile (1)
- +
Must-have verilog systemverilog modules
Created
2015-12-14
261 commits to master branch, last one 4 months ago
Send video/audio over HDMI on an FPGA
Created
2019-08-17
306 commits to master branch, last one 9 months ago
An abstraction library for interfacing EDA tools
Created
2018-05-09
527 commits to main branch, last one 2 days ago
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
Created
2015-04-23
5,423 commits to master branch, last one 2 days ago
Docs, design, firmware, and software for the Haasoscope
Created
2017-12-04
641 commits to master branch, last one 5 months ago
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Created
2023-11-30
443 commits to main branch, last one a day ago
:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
Created
2020-12-14
5 commits to master branch, last one 3 years ago
A Python package to use FPGA development tools programmatically.
Created
2021-02-10
502 commits to main branch, last one 2 years ago
Embedded firmware for ham radio transceivers
Created
2018-12-23
13,922 commits to master branch, last one 2 months ago
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Created
2018-08-17
87 commits to master branch, last one about a year ago
Tools for running FPGA vendor toolchains with Docker
Created
2019-01-04
5 commits to master branch, last one 3 years ago
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Created
2021-08-29
110 commits to main branch, last one 7 months ago
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
This repository has been archived
(exclude archived)
Created
2015-09-18
267 commits to master branch, last one 5 years ago
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
Created
2017-02-21
38 commits to master branch, last one 2 years ago
Portable HyperRAM controller
Created
2022-01-07
164 commits to main_old branch, last one 15 days ago
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Created
2020-04-08
740 commits to master branch, last one 3 years ago
Many peripherals in Verilog ready to use
Created
2023-07-05
362 commits to master branch, last one 4 months ago