15 results found Sort:

pConst
basic_verilog pConst
341
1.5k
unknown
58
Must-have verilog systemverilog modules
hls pwm tcl fifo fpga uart delay altera xilinx encoder uart-tx verilog debounce spi-master synchronizer uart-verilog spi-interface uart-protocol uart-receiver uart-controller
Created 2015-12-14
256 commits to master branch, last one 4 days ago
hdl-util
hdmi hdl-util
107
1.0k
other
43
Send video/audio over HDMI on an FPGA
dvi fpga hdmi audio intel video altera vivado xilinx hdlmake quartus systemverilog
Created 2019-08-17
306 commits to master branch, last one 3 months ago
olofk
edalize olofk
180
597
bsd-2-clause
33
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
523 commits to main branch, last one 14 days ago
f32c
f32c f32c
110
398
bsd-2-clause
50
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
fpga mips riscv altera xilinx arduino lattice
Created 2015-04-23
5,350 commits to master branch, last one 4 days ago
drandyhaas
Haasoscope drandyhaas
37
108
mit
14
Docs, design, firmware, and software for the Haasoscope
fpga eagle altera python verilog open-source oscilloscope open-hardware data-acquisition
Created 2017-12-04
641 commits to master branch, last one 7 days ago
iDoka
awesome-fpga-boards iDoka
11
84
unknown
10
:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
bmc ecp5 fpga jtag qsfp zynq intel pci-e altera xilinx awesome lattice antminer chubby75 ethernet microsoft colorlight awesome-list
Created 2020-12-14
5 commits to master branch, last one 3 years ago
PyFPGA
pyfpga PyFPGA
7
77
gpl-3.0
4
A Python package to use FPGA development tools programmatically.
amd ise tcl fpga ghdl actel intel yosys altera libero python vivado xilinx lattice nextpnr quartus trellis icestorm microchip microsemi
Created 2021-02-10
502 commits to main branch, last one 2 years ago
hukenovs
intfftk hukenovs
25
72
gpl-3.0
7
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
dsp fft fpga vhdl altera vivado xilinx radix-2 verilog cooley-tukey-fft fast-convolutions integer-arithmetic route-optimization fast-fourier-transform digital-signal-processing
Created 2018-08-17
87 commits to master branch, last one about a year ago
ua1arn
hftrx ua1arn
31
69
unknown
11
Embedded firmware for ham radio transceivers
sdr ssb ehci rza1 zynq stm32 altera renesas t113-s3 cortex-a hamradio stm32mp1 allwinner baremetal cortex-a7 cortex-a9 ham-radio sdr-radio bare-metal
Created 2018-12-23
13,022 commits to master branch, last one 8 days ago
halfmanhalftaco
fpga-docker halfmanhalftaco
14
67
unknown
3
Tools for running FPGA vendor toolchains with Docker
fpga vhdl altera xilinx lattice quartus verilog
Created 2019-01-04
5 commits to master branch, last one 2 years ago
BrianHGinc
BrianHG-DDR3-Controller BrianHGinc
29
67
unknown
6
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
hdl ddr3 fpga intel altera xilinx lattice verilog testbenches systemverilog
Created 2021-08-29
110 commits to main branch, last one about a month ago
suoto
vim-hdl suoto
6
61
gpl-3.0
9
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
vhdl altera xilinx verilog modelsim syntastic vim-plugins productivity systemverilog syntax-checker
This repository has been archived (exclude archived)
Created 2015-09-18
267 commits to master branch, last one 4 years ago
hdl-modules
hdl-modules hdl-modules
7
58
bsd-3-clause
4
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
ip amd axi cdc eda rtl asic fifo fpga vhdl intel altera efinix vivado xilinx axi-lite hardware microsemi asynchronous-fifo clock-domain-crossing
Created 2023-11-30
391 commits to main branch, last one 20 hours ago
MJoergen
HyperRAM MJoergen
9
44
mit
7
Portable HyperRAM controller
fpga vhdl artix intel altera avalon questa vivado xilinx lattice quartus hyperram modelsim questasim
Created 2022-01-07
162 commits to main branch, last one 9 days ago
panda5mt
KyogenRV panda5mt
4
42
apache-2.0
3
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
fpga intel riscv rv32i altera chisel risc-v chisel3 avalon-mm
Created 2020-04-08
740 commits to master branch, last one 3 years ago