16 results found Sort:

pConst
basic_verilog pConst
399
1.8k
unknown
60
Must-have verilog systemverilog modules
hls pwm tcl fifo fpga uart delay altera xilinx encoder uart-tx verilog debounce spi-master synchronizer uart-verilog spi-interface uart-protocol uart-receiver uart-controller
Created 2015-12-14
263 commits to master branch, last one 7 days ago
hdl-util
hdmi hdl-util
125
1.1k
other
47
Send video/audio over HDMI on an FPGA
dvi fpga hdmi audio intel video altera vivado xilinx hdlmake quartus systemverilog
Created 2019-08-17
306 commits to master branch, last one about a year ago
olofk
edalize olofk
200
680
bsd-2-clause
31
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
569 commits to main branch, last one 15 days ago
f32c
f32c f32c
105
413
bsd-2-clause
49
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
fpga mips riscv altera xilinx arduino lattice
Created 2015-04-23
5,672 commits to master branch, last one 18 hours ago
hdl-modules
hdl-modules hdl-modules
27
160
bsd-3-clause
6
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
ip amd axi cdc eda rtl asic fifo fpga vhdl intel altera efinix vivado xilinx axi-lite hardware microsemi asynchronous-fifo clock-domain-crossing
Created 2023-11-30
562 commits to main branch, last one 15 days ago
drandyhaas
Haasoscope drandyhaas
40
129
mit
12
Docs, design, firmware, and software for the Haasoscope
fpga eagle altera python verilog open-source oscilloscope open-hardware data-acquisition
Created 2017-12-04
641 commits to master branch, last one 10 months ago
iDoka
awesome-fpga-boards iDoka
12
93
unknown
10
:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
bmc ecp5 fpga jtag qsfp zynq intel pci-e altera xilinx awesome lattice antminer chubby75 ethernet microsoft colorlight awesome-list
Created 2020-12-14
5 commits to master branch, last one 4 years ago
ua1arn
hftrx ua1arn
35
91
unknown
13
Embedded firmware for ham radio transceivers
sdr ssb ehci rza1 zynq stm32 altera renesas t113-s3 cortex-a hamradio stm32mp1 allwinner baremetal cortex-a7 cortex-a9 ham-radio sdr-radio bare-metal
Created 2018-12-23
13,922 commits to master branch, last one 8 months ago
hukenovs
intfftk hukenovs
26
83
gpl-3.0
7
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
dsp fft fpga vhdl altera vivado xilinx radix-2 verilog cooley-tukey-fft fast-convolutions integer-arithmetic route-optimization fast-fourier-transform digital-signal-processing
Created 2018-08-17
87 commits to master branch, last one 2 years ago
BrianHGinc
BrianHG-DDR3-Controller BrianHGinc
32
76
unknown
7
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
hdl ddr3 fpga intel altera xilinx lattice verilog testbenches systemverilog
Created 2021-08-29
110 commits to main branch, last one about a year ago
halfmanhalftaco
fpga-docker halfmanhalftaco
15
75
unknown
4
Tools for running FPGA vendor toolchains with Docker
fpga vhdl altera xilinx lattice quartus verilog
Created 2019-01-04
5 commits to master branch, last one 3 years ago
suoto
vim-hdl suoto
6
60
gpl-3.0
8
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
vhdl altera xilinx verilog modelsim syntastic vim-plugins productivity systemverilog syntax-checker
This repository has been archived (exclude archived)
Created 2015-09-18
267 commits to master branch, last one 5 years ago
hukenovs
fp23fftk hukenovs
18
58
gpl-3.0
8
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
dsp fft fpga vhdl chirp altera matlab octave xilinx ieee754 radix-2 verilog convolution floating-point cooley-tukey-fft fast-convolutions convolution-filter frequency-analysis fast-fourier-transform digital-signal-processing
Created 2017-02-21
38 commits to master branch, last one 2 years ago
MJoergen
HyperRAM MJoergen
14
54
mit
6
Portable HyperRAM controller
fpga vhdl artix intel altera avalon questa vivado xilinx lattice quartus hyperram modelsim questasim
Created 2022-01-07
164 commits to main_old branch, last one 5 months ago
panda5mt
KyogenRV panda5mt
5
45
apache-2.0
2
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
fpga intel riscv rv32i altera chisel risc-v chisel3 avalon-mm
Created 2020-04-08
740 commits to master branch, last one 4 years ago
leonow32
verilog-fpga leonow32
5
36
mit
3
Many peripherals in Verilog ready to use
cpld fpga altera machxo xilinx lattice machxo2 verilog systemverilog
Created 2023-07-05
415 commits to master branch, last one 3 months ago