17 results found Sort:

379
1.6k
unknown
60
Must-have verilog systemverilog modules
Created 2015-12-14
261 commits to master branch, last one 4 months ago
114
1.1k
other
45
Send video/audio over HDMI on an FPGA
Created 2019-08-17
306 commits to master branch, last one 9 months ago
189
636
bsd-2-clause
33
An abstraction library for interfacing EDA tools
Created 2018-05-09
527 commits to main branch, last one 2 days ago
104
403
bsd-2-clause
50
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
Created 2015-04-23
5,423 commits to master branch, last one 2 days ago
Docs, design, firmware, and software for the Haasoscope
Created 2017-12-04
641 commits to master branch, last one 5 months ago
14
105
bsd-3-clause
7
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
Created 2023-11-30
443 commits to main branch, last one a day ago
:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
Created 2020-12-14
5 commits to master branch, last one 3 years ago
10
88
gpl-3.0
3
A Python package to use FPGA development tools programmatically.
Created 2021-02-10
502 commits to main branch, last one 2 years ago
34
79
unknown
12
Embedded firmware for ham radio transceivers
Created 2018-12-23
13,922 commits to master branch, last one 2 months ago
25
76
gpl-3.0
7
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Created 2018-08-17
87 commits to master branch, last one about a year ago
Tools for running FPGA vendor toolchains with Docker
Created 2019-01-04
5 commits to master branch, last one 3 years ago
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
Created 2021-08-29
110 commits to main branch, last one 7 months ago
5
60
gpl-3.0
9
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
This repository has been archived (exclude archived)
Created 2015-09-18
267 commits to master branch, last one 5 years ago
17
54
gpl-3.0
8
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
Created 2017-02-21
38 commits to master branch, last one 2 years ago
Portable HyperRAM controller
Created 2022-01-07
164 commits to main_old branch, last one 15 days ago
4
43
apache-2.0
3
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Created 2020-04-08
740 commits to master branch, last one 3 years ago
Many peripherals in Verilog ready to use
Created 2023-07-05
362 commits to master branch, last one 4 months ago