BrianHGinc / BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Date Created 2021-08-29 (3 years ago)

Commits 110 (last one 8 months ago)

Stargazers 72 (0 this week)

Watchers 7 (0 this week)

Forks 33

License unknown

Ranking

RepositoryStats indexes 595,856 repositories, of these BrianHGinc/BrianHG-DDR3-Controller is ranked #367,915 (38th percentile) for total stargazers, and #271,583 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #102/178.

BrianHGinc/BrianHG-DDR3-Controller is also tagged with popular topics, for these it's ranked: fpga (#330/488), verilog (#203/289)

Other Information

There have been 3 releases, the latest one was published on 2022-06-12 (2 years ago) with the name BrianHG-DDR3-Controller v1.60.

All Topics

hdl ddr3 fpga intel altera xilinx lattice verilog testbenches systemverilog

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

58 commits on the default branch (main) since jan '22

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Languages

The primary language is SystemVerilog but there's also others...

updated: 2024-12-10 @ 12:02pm, id: 400927984 / R_kgDOF-Ws8A