BrianHGinc / BrianHG-DDR3-Controller

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

BrianHGinc
BrianHGinc
Date Created 2021-08-29 (3 years ago)
Commits 110 (last one 11 months ago)
Stargazers 76 (0 this week)
Watchers 7 (0 this week)
Forks 32
License unknown
Ranking

RepositoryStats indexes 630,031 repositories, of these BrianHGinc/BrianHG-DDR3-Controller is ranked #368,929 (41st percentile) for total stargazers, and #260,925 for total watchers. Github reports the primary language for this repository as SystemVerilog, for repositories using this language it is ranked #104/196.

BrianHGinc/BrianHG-DDR3-Controller is also tagged with popular topics, for these it's ranked: fpga (#332/513),  verilog (#202/307)

Other Information

There have been 3 releases, the latest one was published on 2022-06-12 (2 years ago) with the name BrianHG-DDR3-Controller v1.60.

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

58 commits on the default branch (main) since jan '22

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Issue History

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Languages

The primary language is SystemVerilog but there's also others...

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updated: 2025-03-14 @ 04:28am, id: 400927984 / R_kgDOF-Ws8A