54 results found Sort:

open-sdr
openwifi open-sdr
618
3.6k
agpl-3.0
132
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
dma hls sdr csma fpga ofdm wifi zynq linux 802-11 ad9361 xilinx verilog hardware mac80211 openwifi ieee80211 xilinx-fpga analog-devices software-defined-radio
Created 2019-11-08
812 commits to master branch, last one about a month ago
LeiWang1999
FPGA LeiWang1999
620
3.4k
unknown
58
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga pynq vivado xilinx verilog
Created 2020-06-26
85 commits to master branch, last one 2 years ago
pConst
basic_verilog pConst
341
1.5k
unknown
58
Must-have verilog systemverilog modules
hls pwm tcl fifo fpga uart delay altera xilinx encoder uart-tx verilog debounce spi-master synchronizer uart-verilog spi-interface uart-protocol uart-receiver uart-controller
Created 2015-12-14
256 commits to master branch, last one 4 days ago
Xilinx
brevitas Xilinx
177
1.1k
other
34
Brevitas: neural network quantization in PyTorch
ptq qat fpga xilinx pytorch brevitas quantization deep-learning neural-networks hardware-acceleration
Created 2018-07-10
1,290 commits to master branch, last one 3 months ago
trabucayre
openFPGALoader trabucayre
226
1.1k
apache-2.0
35
Universal utility for programming FPGA
arty fpga gowin intel xilinx cyclone lattice bitstream trenz-gowin-littlebee
Created 2019-09-26
1,518 commits to master branch, last one 8 days ago
hdl-util
hdmi hdl-util
107
1.0k
other
43
Send video/audio over HDMI on an FPGA
dvi fpga hdmi audio intel video altera vivado xilinx hdlmake quartus systemverilog
Created 2019-08-17
306 commits to master branch, last one 3 months ago
ultraembedded
biriscv ultraembedded
134
785
apache-2.0
27
32-bit Superscalar RISC-V CPU
cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors
Created 2020-02-10
37 commits to master branch, last one 2 years ago
eugene-tarassov
vivado-risc-v eugene-tarassov
176
753
unknown
33
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
boom fpga kc705 linux riscv vc707 risc-v vivado xilinx arty-a7 genesys2 rocketchip nexys-video
Created 2020-02-15
411 commits to master branch, last one 13 days ago
f4pga
prjxray f4pga
149
744
isc
61
Documenting the Xilinx 7-series bit-stream format.
fpga artix tools artix7 fuzzer vivado xilinx kintex7 bitstream symbiflow toolchain xilinx-fpga
Created 2017-12-16
3,866 commits to master branch, last one 6 days ago
Cr4sh
s6_pcie_microblaze Cr4sh
148
699
unknown
49
PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info
dma fpga uefi pci-e kernel xilinx hyper-v rootkit backdoor hypervisor microblaze
Created 2017-10-09
185 commits to master branch, last one 11 days ago
open-sdr
openwifi-hw open-sdr
219
639
agpl-3.0
41
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware
dma hls rtl sdr csma fpga ofdm vhdl zynq linux wi-fi ad9361 xilinx verilog hardware mac80211 ieee80211 analog-devices software-defined-radio
Created 2019-12-05
333 commits to master branch, last one 6 months ago
olofk
edalize olofk
180
597
bsd-2-clause
33
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
523 commits to main branch, last one 14 days ago
Xilinx
Vitis_Accel_Examples Xilinx
200
475
mit
23
Vitis_Accel_Examples
soc acap zynq alveo vitis xilinx fpga-programming
Created 2019-10-13
1,866 commits to main branch, last one 4 months ago
ZipCPU
wb2axip ZipCPU
94
442
unknown
30
Bus bridges and other odds and ends
fpga gplv3 xilinx axi-bus wishbone wishbone-bus xilinx-vivado
Created 2016-09-21
481 commits to master branch, last one 4 months ago
bperez77
xilinx_axidma bperez77
221
440
mit
41
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic f...
fpga driver xilinx axi-dma axi-vdma fpga-dma zedboard dma-driver linux-driver userspace-dma xilinx-axi-dma xilinx-axi-vdma
Created 2016-03-02
158 commits to master branch, last one 5 years ago
f32c
f32c f32c
110
398
bsd-2-clause
50
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
fpga mips riscv altera xilinx arduino lattice
Created 2015-04-23
5,350 commits to master branch, last one 4 days ago
Xilinx
SDAccel_Examples Xilinx
210
351
other
76
SDAccel Examples
c aws cpp sdx fpga nimbix opencl xilinx sdaccel
Created 2016-08-05
1,731 commits to master branch, last one 3 years ago
WangXuan95
Xilinx-FPGA-PCIe-XDMA-Tutorial WangXuan95
68
328
gpl-3.0
11
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
fpga pcie xdma mpeg2 xilinx pcie-xdma mpeg2-encoder dma-subsystem-for-pcie
Created 2022-12-17
5 commits to main branch, last one 8 months ago
pavel-demin
red-pitaya-notes pavel-demin
199
324
mit
52
Notes on the Red Pitaya Open Source Instrument
dsp mca nmr sdr tcl vna fpga wspr zynq linux radio vitis vivado xilinx verilog redpitaya red-pitaya
Created 2014-12-23
2,907 commits to master branch, last one a day ago
definelicht
hlslib definelicht
51
293
bsd-3-clause
18
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
hpc fpga cmake vitis xilinx sdaccel intel-fpga vivado-hls intel-fpga-opencl high-level-synthesis
Created 2018-02-21
374 commits to master branch, last one about a month ago
lastweek
fpga_readings lastweek
57
272
apache-2.0
29
Recipe for FPGA cooking
hls rtl fpga xilinx verilog vivado-hls
Created 2018-11-06
203 commits to master branch, last one 2 years ago
Xilinx
RapidWright Xilinx
102
271
other
26
Build Customized FPGA Implementations for Vivado
fpga vivado xilinx rapidwright
Created 2017-08-29
1,720 commits to master branch, last one 2 days ago
suoto
hdl_checker suoto
21
184
gpl-3.0
17
Repurposing existing HDL tools to help writing better code
hdl vim ghdl vhdl python xilinx verilog vim-ale coc-nvim modelsim emacs-lsp questasim lsp-server hdl-checker mentor-msim systemverilog xilinx-vivado syntax-checker language-server vivado-simulator
Created 2016-01-23
390 commits to master branch, last one 2 years ago
fpgasystems
Vitis_with_100Gbps_TCP-IP fpgasystems
68
164
unknown
21
100 Gbps TCP/IP stack for Vitis shells
tcp vitis xilinx network-kernel
Created 2020-11-11
15 commits to vitis_2022_1 branch, last one about a month ago
Xtra-Computing
ThunderGP Xtra-Computing
33
135
apache-2.0
10
HLS-based Graph Processing Framework on FPGAs
hls fpgas xilinx accelerators programmability graph-processing graph-analytic-algorithm
Created 2020-04-09
202 commits to master branch, last one about a year ago
Xilinx
xup_vitis_network_example Xilinx
41
127
other
10
VNx: Vitis Network Examples
vnx alveo vitis xilinx alveo-card networking vitis-network
Created 2020-07-28
286 commits to master branch, last one about a month ago
19801201
SpinalHDL_CNN_Accelerator 19801201
32
121
gpl-3.0
5
CNN accelerator implemented with Spinal HDL
cnn fpga yolo xilinx spinalhdl object-detection
Created 2021-12-27
115 commits to dev branch, last one 6 months ago
UCLA-VAST
AutoBridge UCLA-VAST
26
115
mit
11
[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
fpga xilinx floorplan frequency vivado-hls hls-designs hls-compilation
Created 2020-05-13
376 commits to master branch, last one about a year ago
z4yx
petalinux-docker z4yx
64
111
mit
7
Dockerfile to build docker images with Petalinux (Tested on version 2018.3~2021.1)
docker xilinx petalinux
Created 2018-05-25
27 commits to master branch, last one 2 years ago
fischermoseley
manta fischermoseley
7
96
gpl-3.0
4
A configurable and approachable tool for FPGA debugging and rapid prototyping.
fpga debug xilinx verilog icestick icestorm
Created 2023-02-04
403 commits to main branch, last one 19 days ago