open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Date Created 2019-12-05 (4 years ago)

Commits 333 (last one 11 months ago)

Stargazers 696 (0 this week)

Watchers 43 (0 this week)

Forks 237

License agpl-3.0

Ranking

RepositoryStats indexes 579,238 repositories, of these open-sdr/openwifi-hw is ranked #70,136 (88th percentile) for total stargazers, and #49,245 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #33/533.

open-sdr/openwifi-hw is also tagged with popular topics, for these it's ranked: linux (#1,338/5829), fpga (#57/474), hardware (#68/442), verilog (#38/279), hls (#68/250), sdr (#38/196)

Other Information

open-sdr/openwifi-hw has Github issues enabled, there are 8 open issues and 60 closed issues.

All Topics

dma hls rtl sdr csma fpga ofdm vhdl zynq linux wi-fi ad9361 xilinx verilog hardware mac80211 ieee80211 analog-devices software-defined-radio

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

175 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-11-05 @ 06:36pm, id: 226045135 / R_kgDODXkszw