open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

open-sdr
open-sdr
Date Created 2019-12-05 (5 years ago)
Commits 334 (last one 3 months ago)
Stargazers 741 (1 this week)
Watchers 43 (0 this week)
Forks 254
License agpl-3.0
Ranking

RepositoryStats indexes 631,351 repositories, of these open-sdr/openwifi-hw is ranked #70,212 (89th percentile) for total stargazers, and #49,004 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #33/617.

open-sdr/openwifi-hw is also tagged with popular topics, for these it's ranked: linux (#1,351/6195),  fpga (#56/515),  hardware (#70/475),  verilog (#37/307),  hls (#66/259),  sdr (#40/208)

Other Information

open-sdr/openwifi-hw has 2 open pull requests on Github, 42 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 7 open issues and 62 closed issues.

Star History

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

176 commits on the default branch (master) since jan '22

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Yearly Commits

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Issue History

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Languages

The primary language is Verilog but there's also others...

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updated: 2025-03-22 @ 02:45pm, id: 226045135 / R_kgDODXkszw