open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Date Created 2019-12-05 (5 years ago)

Commits 334 (last one 20 days ago)

Stargazers 709 (1 this week)

Watchers 43 (0 this week)

Forks 240

License agpl-3.0

Ranking

RepositoryStats indexes 595,856 repositories, of these open-sdr/openwifi-hw is ranked #70,271 (88th percentile) for total stargazers, and #49,514 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #33/563.

open-sdr/openwifi-hw is also tagged with popular topics, for these it's ranked: linux (#1,339/5945), fpga (#57/488), hardware (#69/451), verilog (#38/289), hls (#68/252), sdr (#38/200)

Other Information

open-sdr/openwifi-hw has Github issues enabled, there are 7 open issues and 62 closed issues.

All Topics

dma hls rtl sdr csma fpga ofdm vhdl zynq linux wi-fi ad9361 xilinx verilog hardware mac80211 ieee80211 analog-devices software-defined-radio

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

176 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-21 @ 12:24pm, id: 226045135 / R_kgDODXkszw