open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Date Created 2019-12-05 (5 years ago)
Commits 334 (last one 2 months ago)
Stargazers 726 (3 this week)
Watchers 44 (0 this week)
Forks 249
License agpl-3.0
Ranking

RepositoryStats indexes 616,861 repositories, of these open-sdr/openwifi-hw is ranked #70,375 (89th percentile) for total stargazers, and #48,527 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #33/601.

open-sdr/openwifi-hw is also tagged with popular topics, for these it's ranked: linux (#1,346/6109),  fpga (#56/503),  hardware (#70/469),  verilog (#37/299),  hls (#66/258),  sdr (#40/207)

Other Information

open-sdr/openwifi-hw has 1 open pull request on Github, 42 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 7 open issues and 62 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

176 commits on the default branch (master) since jan '22

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Yearly Commits

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Issue History

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Languages

The primary language is Verilog but there's also others...

VerilogVerilogTclTclShellShellMATLABMATLAB

updated: 2025-02-18 @ 04:30am, id: 226045135 / R_kgDODXkszw