open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

Date Created 2019-12-05 (4 years ago)

Commits 333 (last one 6 months ago)

Stargazers 639 (3 this week)

Watchers 41 (0 this week)

Forks 219

License agpl-3.0

Ranking

RepositoryStats indexes 523,840 repositories, of these open-sdr/openwifi-hw is ranked #70,663 (87th percentile) for total stargazers, and #51,172 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #34/447.

open-sdr/openwifi-hw is also tagged with popular topics, for these it's ranked: linux (#1,313/5289), fpga (#57/425), hardware (#67/386), verilog (#38/251), hls (#67/227), sdr (#38/182)

Other Information

open-sdr/openwifi-hw has Github issues enabled, there are 7 open issues and 53 closed issues.

All Topics

dma hls rtl sdr csma fpga ofdm vhdl zynq linux wi-fi ad9361 xilinx verilog hardware mac80211 ieee80211 analog-devices software-defined-radio

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

175 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-05-30 @ 05:49pm, id: 226045135 / R_kgDODXkszw