ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

Date Created 2020-02-10 (5 years ago)

Commits 37 (last one 3 years ago)

Stargazers 975 (0 this week)

Watchers 32 (0 this week)

Forks 162

License apache-2.0

Ranking

RepositoryStats indexes 632,768 repositories, of these ultraembedded/biriscv is ranked #54,333 (91st percentile) for total stargazers, and #67,443 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #24/618.

ultraembedded/biriscv is also tagged with popular topics, for these it's ranked: linux (#1,100/6203), fpga (#41/515), verilog (#28/308), cpu (#53/298), risc-v (#34/282)

Other Information

ultraembedded/biriscv has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 20 open issues and 5 closed issues.

All Topics

cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

0 commits on the default branch (master) since jan '22

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2025-03-27 @ 11:21pm, id: 239628306 / R_kgDODkhwEg