ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

Date Created 2020-02-10 (5 years ago)
Commits 37 (last one 3 years ago)
Stargazers 939 (10 this week)
Watchers 30 (0 this week)
Forks 155
License apache-2.0
Ranking

RepositoryStats indexes 615,809 repositories, of these ultraembedded/biriscv is ranked #55,506 (91st percentile) for total stargazers, and #73,658 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #24/600.

ultraembedded/biriscv is also tagged with popular topics, for these it's ranked: linux (#1,112/6102),  fpga (#41/502),  verilog (#28/299),  cpu (#55/295),  risc-v (#34/271)

Other Information

ultraembedded/biriscv has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 20 open issues and 5 closed issues.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

0 commits on the default branch (master) since jan '22

Inactive

No recent commits to this repository

Yearly Commits

Commits to the default branch (master) per year

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Issue History

Total Issues
Open Issues
Closed Issues
25252020151510105500Jul '20Jul '2020212021Jul '21Jul '2120222022Jul '22Jul '2220232023Jul '23Jul '2320242024Jul '24Jul '2420252025

Languages

The primary language is Verilog but there's also others...

VerilogVerilogC++C++MakefileMakefileCC

updated: 2025-02-16 @ 11:19pm, id: 239628306 / R_kgDODkhwEg