ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

Date Created 2020-02-10 (4 years ago)

Commits 37 (last one 3 years ago)

Stargazers 892 (8 this week)

Watchers 30 (0 this week)

Forks 150

License apache-2.0

Ranking

RepositoryStats indexes 596,972 repositories, of these ultraembedded/biriscv is ranked #57,363 (90th percentile) for total stargazers, and #73,304 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #26/564.

ultraembedded/biriscv is also tagged with popular topics, for these it's ranked: linux (#1,137/5950), fpga (#43/489), verilog (#30/291), cpu (#58/286), risc-v (#35/268)

Other Information

ultraembedded/biriscv has 1 open pull request on Github, 0 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 20 open issues and 5 closed issues.

All Topics

cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors

Star History

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Watcher History

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Recent Commit History

0 commits on the default branch (master) since jan '22

No recent commits to this repository

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-25 @ 12:31am, id: 239628306 / R_kgDODkhwEg