ultraembedded / biriscv

32-bit Superscalar RISC-V CPU

Date Created 2020-02-10 (4 years ago)

Commits 37 (last one 2 years ago)

Stargazers 799 (1 this week)

Watchers 29 (0 this week)

Forks 139

License apache-2.0

Ranking

RepositoryStats indexes 534,551 repositories, of these ultraembedded/biriscv is ranked #59,738 (89th percentile) for total stargazers, and #74,255 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #24/459.

ultraembedded/biriscv is also tagged with popular topics, for these it's ranked: linux (#1,150/5385), fpga (#42/435), verilog (#30/257), risc-v (#33/225)

Other Information

ultraembedded/biriscv has Github issues enabled, there are 19 open issues and 5 closed issues.

All Topics

cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors

Star History

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Recent Commit History

0 commits on the default branch (master) since jan '22

No recent commits to this repository

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-06-28 @ 06:49am, id: 239628306 / R_kgDODkhwEg