14 results found Sort:

darklife
darkriscv darklife
290
2.1k
bsd-3-clause
94
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design
Created 2018-08-19
343 commits to master branch, last one about a month ago
ultraembedded
riscv ultraembedded
238
1.3k
bsd-3-clause
52
RISC-V CPU Core (RV32IM)
cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor
Created 2014-08-31
48 commits to master branch, last one 3 years ago
sysprog21
shecc sysprog21
123
1.1k
bsd-2-clause
25
A self-hosting and educational C optimizing compiler
c arm elf qemu armv7 linux riscv rv32i risc-v rv32im compiler ssa-form self-hosting cross-compiler compiler-optimization
Created 2020-08-30
303 commits to master branch, last one 3 days ago
ultraembedded
biriscv ultraembedded
150
890
apache-2.0
30
32-bit Superscalar RISC-V CPU
cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors
Created 2020-02-10
37 commits to master branch, last one 3 years ago
syntacore
scr1 syntacore
282
883
other
52
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog
Created 2017-05-09
67 commits to master branch, last one about a month ago
WangXuan95
USTC-RVSoC WangXuan95
75
366
gpl-3.0
14
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。
cpu rtl soc fpga riscv rv32i risc-v verilog softcore systemverilog
Created 2019-02-05
66 commits to master branch, last one about a year ago
riscv-steel
riscv-steel riscv-steel
20
162
mit
12
RISC-V 32-bit microcontroller developed in Verilog
cpu mcu spi core gpio uart riscv rv32i steel zicsr risc-v processor system-on-chip microcontroller
Created 2020-05-03
951 commits to main branch, last one 2 months ago
stnolting
riscv-gcc-prebuilt stnolting
10
94
gpl-2.0
7
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
gcc linux riscv rv32i risc-v neorv32 prebuilt-binaries
Created 2021-01-19
65 commits to main branch, last one 9 months ago
AngeloJacobo
RISC-V AngeloJacobo
6
74
mit
7
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
cpu rv32 riscv rv32i risc-v verilog 5-stage-pipeline formal-verification
Created 2022-03-04
407 commits to main branch, last one about a year ago
maikmerten
spu32 maikmerten
13
66
mit
14
Small Processing Unit 32: A compact RV32I CPU written in Verilog
fpga ice40 rv32i risc-v verilog icestorm risc-processor system-on-chip
Created 2018-02-09
632 commits to master branch, last one 2 years ago
aignacio
nox aignacio
6
61
mit
7
RISC-V Nox core
rv32i risc-v
Created 2021-12-12
215 commits to master branch, last one 4 months ago
panda5mt
KyogenRV panda5mt
5
44
apache-2.0
3
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
fpga intel riscv rv32i altera chisel risc-v chisel3 avalon-mm
Created 2020-04-08
740 commits to master branch, last one 3 years ago
FelipeFFerreira
ITA-CORES FelipeFFerreira
3
40
other
2
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
asic chip rv32i risc-v femtorv32 framework physical-design physical-design-automation
Created 2023-06-13
121 commits to master branch, last one about a year ago
martinKindall
risc-v-single-cycle martinKindall
2
36
unknown
4
A Single Cycle Risc-V 32 bit CPU
riscv rv32i basys3 riscv32 basys3-fpga systemverilog riscv-assembly single-cycle-processor
Created 2022-12-21
29 commits to main branch, last one about a year ago