13 results found Sort:

darklife
darkriscv darklife
271
1.9k
bsd-3-clause
86
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
cpu rtl core fpga riscv rv32e rv32i risc-v verilog softcore processor processor-design
Created 2018-08-19
286 commits to master branch, last one 7 days ago
ultraembedded
riscv ultraembedded
211
1.1k
bsd-3-clause
48
RISC-V CPU Core (RV32IM)
cpu asic fpga rv32i risc-v rv32im verilog verilator riscv-linux verification pipeline-processor
Created 2014-08-31
48 commits to master branch, last one 2 years ago
sysprog21
shecc sysprog21
110
1.1k
bsd-2-clause
28
A self-hosting and educational C optimizing compiler
c arm elf qemu armv7 linux riscv rv32i risc-v rv32im compiler self-hosting cross-compiler compiler-optimization
Created 2020-08-30
239 commits to master branch, last one about a month ago
syntacore
scr1 syntacore
267
800
other
50
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
ip rtl core riscv rv32e rv32i risc-v rv32emc rv32imc verilog
Created 2017-05-09
65 commits to master branch, last one about a month ago
ultraembedded
biriscv ultraembedded
134
790
apache-2.0
27
32-bit Superscalar RISC-V CPU
cpu asic fpga linux rv32i risc-v rv32im xilinx artix-7 verilog coremark in-order verilator riscv-linux superscalar branch-prediction pipelined-processors
Created 2020-02-10
37 commits to master branch, last one 2 years ago
WangXuan95
USTC-RVSoC WangXuan95
69
327
gpl-3.0
13
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
cpu rtl soc fpga riscv rv32i risc-v verilog softcore systemverilog
Created 2019-02-05
66 commits to master branch, last one 9 months ago
riscv-steel
riscv-steel riscv-steel
17
116
mit
12
Open source RISC-V microcontroller unit for FPGAs written in Verilog
ip core uart cores riscv rv32i zicsr risc-v processors embedded-systems microcontrollers systems-on-chip-design
Created 2020-05-03
841 commits to main branch, last one 3 days ago
stnolting
riscv-gcc-prebuilt stnolting
8
78
gpl-2.0
7
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
gcc linux riscv rv32i risc-v neorv32 prebuilt-binaries
Created 2021-01-19
65 commits to main branch, last one 2 months ago
maikmerten
spu32 maikmerten
11
61
mit
14
Small Processing Unit 32: A compact RV32I CPU written in Verilog
fpga ice40 rv32i risc-v verilog icestorm risc-processor system-on-chip
Created 2018-02-09
632 commits to master branch, last one 2 years ago
aignacio
nox aignacio
6
51
mit
6
RISC-V Nox core
rv32i risc-v
Created 2021-12-12
208 commits to master branch, last one 2 months ago
AngeloJacobo
RISC-V AngeloJacobo
3
48
mit
5
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
cpu rv32 riscv rv32i risc-v verilog 5-stage-pipeline formal-verification
Created 2022-03-04
407 commits to main branch, last one 5 months ago
panda5mt
KyogenRV panda5mt
4
42
apache-2.0
3
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
fpga intel riscv rv32i altera chisel risc-v chisel3 avalon-mm
Created 2020-04-08
740 commits to master branch, last one 3 years ago
FelipeFFerreira
ITA-CORES FelipeFFerreira
3
35
other
2
RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
asic chip rv32i risc-v femtorv32 framework physical-design physical-design-automation
Created 2023-06-13
121 commits to master branch, last one 6 months ago