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AngeloJacobo
RISC-V AngeloJacobo
4
59
mit
7
Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
cpu rv32 riscv rv32i risc-v verilog 5-stage-pipeline formal-verification
Created 2022-03-04
407 commits to main branch, last one 9 months ago