AngeloJacobo / RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Date Created 2022-03-04 (2 years ago)
Commits 407 (last one about a year ago)
Stargazers 80 (0 this week)
Watchers 7 (0 this week)
Forks 5
License mit
Ranking

RepositoryStats indexes 617,630 repositories, of these AngeloJacobo/RISC-V is ranked #351,025 (43rd percentile) for total stargazers, and #274,000 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #289/601.

AngeloJacobo/RISC-V is also tagged with popular topics, for these it's ranked: verilog (#194/299),  cpu (#206/295),  risc-v (#159/271),  riscv (#117/175)

Other Information

There have been 7 releases, the latest one was published on 2022-06-23 (2 years ago) with the name v5.0 Five Stage Pipelined Architecture.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

398 commits on the default branch (main) since jan '22

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Yearly Commits

Commits to the default branch (main) per year

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Issue History

Total Issues
Open Issues
Closed Issues
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Languages

The primary language is Verilog but there's also others...

VerilogVerilogAssemblyAssemblyCCShellShellTclTclStataStataSystemVerilogSystemVerilog

updated: 2025-02-18 @ 02:43am, id: 466168448 / R_kgDOG8kqgA