AngeloJacobo / RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Date Created 2022-03-04 (2 years ago)

Commits 407 (last one about a year ago)

Stargazers 74 (1 this week)

Watchers 7 (0 this week)

Forks 6

License mit

Ranking

RepositoryStats indexes 595,890 repositories, of these AngeloJacobo/RISC-V is ranked #360,923 (39th percentile) for total stargazers, and #271,563 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #294/563.

AngeloJacobo/RISC-V is also tagged with popular topics, for these it's ranked: verilog (#197/289), cpu (#206/285), risc-v (#163/268), riscv (#116/167)

Other Information

There have been 7 releases, the latest one was published on 2022-06-23 (2 years ago) with the name v5.0 Five Stage Pipelined Architecture.

All Topics

cpu rv32 riscv rv32i risc-v verilog 5-stage-pipeline formal-verification

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Github watchers over time, collection started in '23

Recent Commit History

398 commits on the default branch (main) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-12-20 @ 07:50am, id: 466168448 / R_kgDOG8kqgA