AngeloJacobo / RISC-V

Design implementation of the RV32I Core in Verilog HDL with Zicsr extension

Date Created 2022-03-04 (2 years ago)

Commits 407 (last one 5 months ago)

Stargazers 47 (0 this week)

Watchers 4 (0 this week)

Forks 3

License mit

Ranking

RepositoryStats indexes 523,840 repositories, of these AngeloJacobo/RISC-V is ranked #438,812 (16th percentile) for total stargazers, and #351,116 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #355/447.

AngeloJacobo/RISC-V is also tagged with popular topics, for these it's ranked: verilog (#223/251), risc-v (#186/221), riscv (#121/146)

Other Information

There have been 7 releases, the latest one was published on 2022-06-23 (about a year ago) with the name v5.0 Five Stage Pipelined Architecture.

All Topics

cpu rv32 riscv rv32i risc-v verilog 5-stage-pipeline formal-verification

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

398 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-05-29 @ 12:24pm, id: 466168448 / R_kgDOG8kqgA