5 results found Sort:

buserror
simavr buserror
374
1.6k
gpl-3.0
72
simavr is a lean, mean and hackable AVR simulator for linux & OSX
c simavr avr-gcc gtkwave debugger embedded avr-simulator
Created 2012-05-14
1,165 commits to master branch, last one 3 months ago
yne
vcd yne
12
116
mit
7
VCD file (Value Change Dump) command line viewer
cli vcd vhdl gtkwave
Created 2014-11-22
30 commits to master branch, last one 2 years ago
dpretet
svut dpretet
17
76
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
tdd vcd flow foss svut python surfer gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies
Created 2017-03-12
195 commits to master branch, last one 5 months ago
tscheipel
HaDes-V tscheipel
2
40
mit
1
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
riscv rv32i risc-v vivado gtkwave pipelines verilator c-programming systemverilog open-education system-verilog processor-design university-course assembly-programming computer-architecture microcontroller-design processor-architecture hardware-software-codesign open-educational-resources
Created 2024-12-14
4 commits to main branch, last one about a month ago
maazm007
vsdsquadron-mini-internship maazm007
15
26
unknown
1
VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.
yosys risc-v gtkwave objdump iverilog verilog-hdl vlsi-design gcc-complier
Created 2024-04-20
56 commits to VSD branch, last one 10 months ago