4 results found Sort:

buserror
simavr buserror
371
1.6k
gpl-3.0
73
simavr is a lean, mean and hackable AVR simulator for linux & OSX
c simavr avr-gcc gtkwave debugger embedded avr-simulator
Created 2012-05-14
1,165 commits to master branch, last one 9 days ago
yne
vcd yne
12
112
mit
8
VCD file (Value Change Dump) command line viewer
cli vcd vhdl gtkwave
Created 2014-11-22
30 commits to master branch, last one 2 years ago
dpretet
svut dpretet
16
72
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
tdd vcd flow foss svut python surfer gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies
Created 2017-03-12
195 commits to master branch, last one 2 months ago
tscheipel
HaDes-V tscheipel
1
26
mit
1
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
riscv rv32i risc-v vivado gtkwave pipelines verilator c-programming systemverilog open-education system-verilog processor-design university-course assembly-programming computer-architecture microcontroller-design processor-architecture hardware-software-codesign open-educational-resources
Created 2024-12-14
3 commits to main branch, last one 12 days ago