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simavr is a lean, mean and hackable AVR simulator for linux & OSX
Created
2012-05-14
1,148 commits to master branch, last one 2 months ago
VCD file (Value Change Dump) command line viewer
Created
2014-11-22
30 commits to master branch, last one about a year ago
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Created
2017-03-12
179 commits to master branch, last one 2 days ago