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372
1.6k
gpl-3.0
73
simavr is a lean, mean and hackable AVR simulator for linux & OSX
Created 2012-05-14
1,165 commits to master branch, last one 2 months ago
12
113
mit
8
VCD file (Value Change Dump) command line viewer
Created 2014-11-22
30 commits to master branch, last one 2 years ago
16
73
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Created 2017-03-12
195 commits to master branch, last one 4 months ago
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
Created 2024-12-14
4 commits to main branch, last one 24 days ago