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edalize olofk

191

643

bsd-2-clause

33

An abstraction library for interfacing EDA tools

Created 2018-05-09

542 commits to main branch, last one 7 days ago

vscode-verilog-hdl-support mshr-h

78

296

mit

11

HDL support for VS Code

svls ctags vivado vscode verilog iverilog modelsim verilator verilog-hdl hacktoberfest systemverilog icarus-verilog systemverilog-support bluespec-systemverilog language-server-client

Created 2015-12-10

559 commits to main branch, last one 12 days ago

async_fifo dpretet

76

264

other

11

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain

Created 2017-03-28

49 commits to master branch, last one 7 months ago

xcrypto scarv

10

92

mit

13

XCrypto: a cryptographic ISE for RISC-V

cpu ise riscv yosys crypto risc-v verilog xcrypto hardware mit-license open-source cryptography icarus-verilog research-project formal-verification hardware-acceleration instruction-set-architecture

This repository has been archived (exclude archived)

Created 2018-07-30

874 commits to master branch, last one about a year ago

svut dpretet

16

70

mit

3

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

tdd vcd flow foss svut python surfer gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies

Created 2017-03-12

195 commits to master branch, last one about a month ago

neorv32-verilog stnolting

13

66

bsd-3-clause

9

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga ghdl neorv32 verilog icarus-verilog

Created 2022-08-27

312 commits to main branch, last one 2 days ago