6 results found Sort:

200
681
bsd-2-clause
31
An abstraction library for interfacing EDA tools
Created 2018-05-09
569 commits to main branch, last one 17 days ago
83
323
other
11
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
Created 2017-03-28
49 commits to master branch, last one 12 months ago
10
92
mit
12
XCrypto: a cryptographic ISE for RISC-V
This repository has been archived (exclude archived)
Created 2018-07-30
874 commits to master branch, last one 2 years ago
18
80
bsd-3-clause
9
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Created 2022-08-27
389 commits to main branch, last one a day ago
17
77
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
Created 2017-03-12
195 commits to master branch, last one 5 months ago