stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Date Created 2022-08-27 (2 years ago)

Commits 385 (last one 7 hours ago)

Stargazers 80 (1 this week)

Watchers 9 (0 this week)

Forks 18

License bsd-3-clause

Ranking

RepositoryStats indexes 636,050 repositories, of these stnolting/neorv32-verilog is ranked #358,757 (44th percentile) for total stargazers, and #218,411 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #94/201.

stnolting/neorv32-verilog is also tagged with popular topics, for these it's ranked: fpga (#321/522), verilog (#199/312)

Other Information

Homepage URL: https://github.com/stnolting/neorv32

All Topics

asic fpga ghdl neorv32 verilog icarus-verilog

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385 commits on the default branch (main) since jan '22

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The primary language is VHDL but there's also others...

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updated: 2025-04-07 @ 09:51am, id: 529618104 / R_kgDOH5FUuA