stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

Date Created 2022-08-27 (2 years ago)

Commits 321 (last one 6 days ago)

Stargazers 70 (0 this week)

Watchers 9 (0 this week)

Forks 13

License bsd-3-clause

Ranking

RepositoryStats indexes 595,856 repositories, of these stnolting/neorv32-verilog is ranked #374,828 (37th percentile) for total stargazers, and #225,801 for total watchers. Github reports the primary language for this repository as VHDL, for repositories using this language it is ranked #100/183.

stnolting/neorv32-verilog is also tagged with popular topics, for these it's ranked: fpga (#337/488), verilog (#207/289)

Other Information

Homepage URL: https://github.com/stnolting/neorv32

All Topics

asic fpga ghdl neorv32 verilog icarus-verilog

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

321 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The primary language is VHDL but there's also others...

Opengraph Image

updated: 2024-12-21 @ 01:40am, id: 529618104 / R_kgDOH5FUuA