dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Date Created 2017-03-28 (7 years ago)

Commits 49 (last one 10 months ago)

Stargazers 307 (3 this week)

Watchers 11 (0 this week)

Forks 83

License other

Ranking

RepositoryStats indexes 622,366 repositories, of these dpretet/async_fifo is ranked #137,007 (78th percentile) for total stargazers, and #194,421 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #76/607.

dpretet/async_fifo is also tagged with popular topics, for these it's ranked: async (#319/968), fpga (#111/505), verilog (#75/302)

Other Information

dpretet/async_fifo has 1 open pull request on Github, 5 pull requests have been merged over the lifetime of the repository.

There have been 5 releases, the latest one was published on 2024-04-18 (10 months ago) with the name Maintenance.

All Topics

cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

6 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2025-03-03 @ 12:14pm, id: 86497447 / R_kgDOBSfYpw