dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Date Created 2017-03-28 (7 years ago)

Commits 49 (last one 2 months ago)

Stargazers 223 (3 this week)

Watchers 10 (0 this week)

Forks 70

License other

Ranking

RepositoryStats indexes 534,551 repositories, of these dpretet/async_fifo is ranked #155,673 (71st percentile) for total stargazers, and #199,760 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #93/459.

dpretet/async_fifo is also tagged with popular topics, for these it's ranked: async (#358/864), fpga (#124/435), verilog (#86/257)

Other Information

dpretet/async_fifo has 1 open pull request on Github, 5 pull requests have been merged over the lifetime of the repository.

There have been 5 releases, the latest one was published on 2024-04-18 (2 months ago) with the name Maintenance.

All Topics

cdc hdl asic fifo fpga async verilog synthesis verilator fifo-cache fifo-queue asic-design verilog-hdl verification icarus-verilog cross-clock-domain

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

6 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-06-29 @ 08:09am, id: 86497447 / R_kgDOBSfYpw