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dpretet
svut dpretet
15
64
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
tdd vcd flow foss svut python gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies
Created 2017-03-12
179 commits to master branch, last one 2 days ago