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dpretet
svut dpretet
16
70
mit
3
SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!
tdd vcd flow foss svut python surfer gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies
Created 2017-03-12
195 commits to master branch, last one 16 days ago