dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Date Created 2017-03-12 (7 years ago)

Commits 195 (last one 3 months ago)

Stargazers 72 (0 this week)

Watchers 3 (0 this week)

Forks 16

License mit

Ranking

RepositoryStats indexes 609,425 repositories, of these dpretet/svut is ranked #373,819 (39th percentile) for total stargazers, and #432,193 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #71,208/122,950.

dpretet/svut is also tagged with popular topics, for these it's ranked: python (#15,619/22740), simulation (#689/1037), simulator (#242/345), verilog (#207/297), tdd (#193/255), foss (#145/198)

Other Information

There have been 11 releases, the latest one was published on 2024-10-21 (3 months ago) with the name v1.10.0: Support FST waveform format.

All Topics

tdd vcd flow foss svut python surfer gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies

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Recent Commit History

48 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-12-07 @ 01:45am, id: 84708238 / R_kgDOBQyLjg