dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Date Created 2017-03-12 (7 years ago)

Commits 195 (last one 16 days ago)

Stargazers 70 (0 this week)

Watchers 3 (0 this week)

Forks 16

License mit

Ranking

RepositoryStats indexes 579,555 repositories, of these dpretet/svut is ranked #367,059 (37th percentile) for total stargazers, and #420,420 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #69,051/115,123.

dpretet/svut is also tagged with popular topics, for these it's ranked: python (#15,412/21870), simulation (#670/996), simulator (#237/332), verilog (#200/280), foss (#142/189)

Other Information

There have been 11 releases, the latest one was published on 2024-10-21 (16 days ago) with the name v1.10.0: Support FST waveform format.

All Topics

tdd vcd flow foss svut python surfer gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies

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Github watchers over time, collection started in '23

Recent Commit History

48 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-10-23 @ 02:21pm, id: 84708238 / R_kgDOBQyLjg