dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Date Created 2017-03-12 (7 years ago)

Commits 179 (last one a day ago)

Stargazers 64 (0 this week)

Watchers 3 (0 this week)

Forks 15

License mit

Ranking

RepositoryStats indexes 534,880 repositories, of these dpretet/svut is ranked #366,815 (31st percentile) for total stargazers, and #399,187 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #67,667/103,597.

dpretet/svut is also tagged with popular topics, for these it's ranked: python (#15,321/20457), simulation (#664/919), simulator (#234/311), verilog (#196/257), foss (#134/172)

Other Information

There have been 8 releases, the latest one was published on 2024-06-27 (4 days ago) with the name v1.9.1.

All Topics

tdd vcd flow foss svut python gtkwave verilog testcase simulator verilator simulation mit-license systemverilog tdd-utilities icarus-verilog verification-methodologies

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Recent Commit History

32 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

updated: 2024-06-30 @ 08:39am, id: 84708238 / R_kgDOBQyLjg