dpretet / svut

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

Date Created 2017-03-12 (7 years ago)
Commits 195 (last one 4 months ago)
Stargazers 73 (0 this week)
Watchers 3 (0 this week)
Forks 16
License mit
Ranking

RepositoryStats indexes 618,350 repositories, of these dpretet/svut is ranked #374,607 (39th percentile) for total stargazers, and #434,053 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #71,519/125,168.

dpretet/svut is also tagged with popular topics, for these it's ranked: python (#15,646/22999),  simulation (#692/1046),  simulator (#244/347),  verilog (#205/299),  tdd (#193/255),  foss (#148/204)

Other Information

There have been 11 releases, the latest one was published on 2024-10-21 (4 months ago) with the name v1.10.0: Support FST waveform format.

Star History

Github stargazers over time

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Watcher History

Github watchers over time, collection started in '23

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Recent Commit History

48 commits on the default branch (master) since jan '22

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Issue History

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Languages

The primary language is Python but there's also others...

PythonPythonSystemVerilogSystemVerilogShellShellVerilogVerilogC++C++

updated: 2025-02-22 @ 12:27am, id: 84708238 / R_kgDOBQyLjg