10 results found Sort:

olofk
edalize olofk
194
651
bsd-2-clause
33
An abstraction library for interfacing EDA tools
eda fpga ghdl vhdl fossi yosys altera vivado xilinx lattice verilog icestorm modelsim spyglass synthesis verilator simulation riviera-pro systemverilog icarus-verilog
Created 2018-05-09
549 commits to main branch, last one 24 days ago
mshr-h
vscode-verilog-hdl-support mshr-h
79
302
mit
11
HDL support for VS Code
svls ctags vivado vscode verilog iverilog modelsim verilator verilog-hdl hacktoberfest systemverilog icarus-verilog systemverilog-support bluespec-systemverilog language-server-client
Created 2015-12-10
559 commits to main branch, last one about a month ago
suoto
hdl_checker suoto
23
196
gpl-3.0
17
Repurposing existing HDL tools to help writing better code
hdl vim ghdl vhdl python xilinx verilog vim-ale coc-nvim modelsim emacs-lsp questasim lsp-server hdl-checker mentor-msim systemverilog xilinx-vivado syntax-checker language-server vivado-simulator
Created 2016-01-23
390 commits to master branch, last one 2 years ago
loykylewong
FPGA-Application-Development-and-Simulation loykylewong
30
127
mit
5
《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
cic dds dsp fft fir i2c i2s iir qam spi axi4 fpga uart adpll cordic verilog modelsim modulation systemverilog digital-signal-processing
Created 2019-05-31
26 commits to master branch, last one 2 months ago
Paebbels
JSON-for-VHDL Paebbels
16
76
other
14
A JSON library implemented in VHDL.
fpga ghdl json vhdl parser xilinx lattice modelsim questasim synthesis fileformat simulation
Created 2015-09-01
61 commits to master branch, last one 2 years ago
suoto
vim-hdl suoto
5
60
gpl-3.0
9
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
vhdl altera xilinx verilog modelsim syntastic vim-plugins productivity systemverilog syntax-checker
This repository has been archived (exclude archived)
Created 2015-09-18
267 commits to master branch, last one 5 years ago
RomeoMe5
DDLM RomeoMe5
42
53
mit
4
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
alu fsm hse tcl ddlm labs miem mips quartus terasic verilog modelsim dmk-press schoolmips verilog-book quartus-prime system-verilog verilog-designs mips-architecture terasic-de10-lite
Created 2019-12-30
60 commits to master branch, last one about a year ago
prajwalgekkouga
AHB-to-APB-Bridge prajwalgekkouga
14
52
unknown
1
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equiva...
ahb apb amba fpga digital verilog modelsim verilog-project
Created 2022-10-04
6 commits to main branch, last one 2 years ago
MJoergen
HyperRAM MJoergen
11
50
mit
7
Portable HyperRAM controller
fpga vhdl artix intel altera avalon questa vivado xilinx lattice quartus hyperram modelsim questasim
Created 2022-01-07
164 commits to main_old branch, last one 2 months ago
DOUDIU
Hardware-Implementation-of-the-Canny-Edge-Detection-Algorithm DOUDIU
0
32
unknown
1
The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient to replicate using any simulator and any of the available FPGA b...
fpga canny vivado modelsim
Created 2022-07-28
27 commits to main branch, last one 8 months ago