prajwalgekkouga / AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Date Created 2022-10-04 (2 years ago)

Commits 6 (last one 2 years ago)

Stargazers 49 (0 this week)

Watchers 1 (0 this week)

Forks 12

License unknown

Ranking

RepositoryStats indexes 579,238 repositories, of these prajwalgekkouga/AHB-to-APB-Bridge is ranked #465,288 (20th percentile) for total stargazers, and #532,159 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #402/533.

prajwalgekkouga/AHB-to-APB-Bridge is also tagged with popular topics, for these it's ranked: fpga (#402/474), verilog (#241/279)

Other Information

prajwalgekkouga/AHB-to-APB-Bridge has Github issues enabled, there is 1 open issue and 0 closed issues.

All Topics

ahb apb amba fpga digital verilog modelsim verilog-project

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6 commits on the default branch (main) since jan '22

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The only known language in this repository is Verilog

updated: 2024-10-28 @ 10:17pm, id: 545412126 / R_kgDOIIJUHg