prajwalgekkouga / AHB-to-APB-Bridge

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Date Created 2022-10-04 (2 years ago)

Commits 6 (last one 2 years ago)

Stargazers 56 (1 this week)

Watchers 1 (0 this week)

Forks 14

License unknown

Ranking

RepositoryStats indexes 624,936 repositories, of these prajwalgekkouga/AHB-to-APB-Bridge is ranked #451,092 (28th percentile) for total stargazers, and #551,686 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #397/609.

prajwalgekkouga/AHB-to-APB-Bridge is also tagged with popular topics, for these it's ranked: fpga (#397/507), verilog (#240/304)

Other Information

prajwalgekkouga/AHB-to-APB-Bridge has Github issues enabled, there is 1 open issue and 0 closed issues.

All Topics

ahb apb amba fpga digital verilog modelsim verilog-project

Star History

Github stargazers over time

Watcher History

Github watchers over time, collection started in '23

Recent Commit History

6 commits on the default branch (main) since jan '22

Yearly Commits

Commits to the default branch (main) per year

Issue History

Languages

The only known language in this repository is Verilog

updated: 2025-03-06 @ 06:16am, id: 545412126 / R_kgDOIIJUHg