5 results found Sort:

verilator
verilator verilator
555
2.3k
lgpl-3.0
73
Verilator open-source SystemVerilog simulator and lint system
cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator
Created 2019-06-13
7,013 commits to master branch, last one 21 hours ago
esynr3z
corsair esynr3z
29
92
mit
12
Control and Status Register map generator for HDL projects
asic fpga python verilog system-verilog
Created 2020-11-06
240 commits to master branch, last one about a year ago
taneroksuz
fpu taneroksuz
9
50
apache-2.0
2
IEEE 754 floating point library in system-verilog and vhdl
fpu fpga vhdl risc-v verilog hardware system-verilog
Created 2019-07-06
123 commits to main branch, last one 22 days ago
RomeoMe5
DDLM RomeoMe5
39
49
mit
3
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
alu fsm hse tcl ddlm labs miem mips quartus terasic verilog modelsim dmk-press schoolmips verilog-book quartus-prime system-verilog verilog-designs mips-architecture terasic-de10-lite
Created 2019-12-30
60 commits to master branch, last one 9 months ago
Eyantra698Sumanto
Spice-to-Verilog-Converter Eyantra698Sumanto
2
11
gpl-3.0
1
Spice to Verilog Converter
spice analog verilog verilog-hdl system-verilog
Created 2022-06-03
11 commits to main branch, last one about a year ago