5 results found Sort:

verilator
verilator verilator
644
2.8k
lgpl-3.0
73
Verilator open-source SystemVerilog simulator and lint system
cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator
Created 2019-06-13
7,721 commits to master branch, last one 13 hours ago
esynr3z
corsair esynr3z
37
113
mit
12
Control and Status Register map generator for HDL projects
asic fpga python verilog system-verilog
Created 2020-11-06
240 commits to master branch, last one about a year ago
RomeoMe5
DDLM RomeoMe5
42
54
mit
3
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
alu fsm hse tcl ddlm labs miem mips quartus terasic verilog modelsim dmk-press schoolmips verilog-book quartus-prime system-verilog verilog-designs mips-architecture terasic-de10-lite
Created 2019-12-30
60 commits to master branch, last one about a year ago
tscheipel
HaDes-V tscheipel
2
40
mit
1
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz...
riscv rv32i risc-v vivado gtkwave pipelines verilator c-programming systemverilog open-education system-verilog processor-design university-course assembly-programming computer-architecture microcontroller-design processor-architecture hardware-software-codesign open-educational-resources
Created 2024-12-14
4 commits to main branch, last one about a month ago
Eyantra698Sumanto
Spice-to-Verilog-Converter Eyantra698Sumanto
1
12
gpl-3.0
1
Spice to Verilog Converter
spice analog verilog verilog-hdl system-verilog
Created 2022-06-03
11 commits to main branch, last one 2 years ago