esynr3z / corsair

Control and Status Register map generator for HDL projects

Date Created 2020-11-06 (4 years ago)

Commits 240 (last one about a year ago)

Stargazers 99 (0 this week)

Watchers 12 (0 this week)

Forks 35

License mit

Ranking

RepositoryStats indexes 579,238 repositories, of these esynr3z/corsair is ranked #290,374 (50th percentile) for total stargazers, and #177,082 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #53,566/115,001.

esynr3z/corsair is also tagged with popular topics, for these it's ranked: python (#12,723/21862), fpga (#249/474), verilog (#148/279)

Other Information

esynr3z/corsair has 12 open pull requests on Github, 16 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 40 open issues and 14 closed issues.

Homepage URL: https://corsair.readthedocs.io

All Topics

asic fpga python verilog system-verilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

27 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Python but there's also others...

updated: 2024-11-05 @ 12:15pm, id: 310674835 / R_kgDOEoSFkw