esynr3z / corsair

Control and Status Register map generator for HDL projects

Date Created 2020-11-06 (3 years ago)

Commits 240 (last one about a year ago)

Stargazers 92 (0 this week)

Watchers 12 (0 this week)

Forks 30

License mit

Ranking

RepositoryStats indexes 535,551 repositories, of these esynr3z/corsair is ranked #288,092 (46th percentile) for total stargazers, and #172,494 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #52,230/103,734.

esynr3z/corsair is also tagged with popular topics, for these it's ranked: python (#12,623/20472), fpga (#247/435), verilog (#149/257)

Other Information

esynr3z/corsair has 9 open pull requests on Github, 16 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 21 open issues and 10 closed issues.

Homepage URL: https://corsair.readthedocs.io

All Topics

asic fpga python verilog system-verilog

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

27 commits on the default branch (master) since jan '22

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Issue History

Languages

The primary language is Python but there's also others...

updated: 2024-07-03 @ 06:01am, id: 310674835 / R_kgDOEoSFkw