15 results found Sort:

verilator
verilator verilator
654
2.8k
lgpl-3.0
72
Verilator open-source SystemVerilog simulator and lint system
cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator
Created 2019-06-13
7,811 commits to master branch, last one a day ago
sergeykhbr
riscv_vhdl sergeykhbr
106
649
apache-2.0
51
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
qt cpu soc vhdl riscv systemc debugger simulator
Created 2015-11-08
1,342 commits to master branch, last one 5 months ago
accellera-official
systemc accellera-official
163
545
apache-2.0
43
SystemC Reference Implementation
cpp tlm systemc
Created 2019-07-25
4,178 commits to main branch, last one 26 days ago
mariusmm
RISC-V-TLM mariusmm
75
303
gpl-3.0
18
RISC-V SystemC-TLM simulator
tlm2 riscv risc-v systemc
Created 2018-09-10
367 commits to master branch, last one 11 months ago
intel
systemc-compiler intel
40
270
other
16
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
hls llvm clang systemc hardware-designs
Created 2020-10-16
153 commits to main branch, last one 13 days ago
davidepatti
noxim davidepatti
132
265
unknown
17
Network on Chip Simulator
noc noxim systemc simulation university network-analysis
Created 2015-03-23
679 commits to master branch, last one about a year ago
Xilinx
libsystemctlm-soc Xilinx
71
242
other
21
SystemC/TLM-2.0 Co-simulation framework
qemu tlm2 systemc co-simulation
Created 2016-10-27
588 commits to master branch, last one 5 months ago
Nic30
hwt Nic30
28
210
mit
17
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
hcl hls rtl uvm fpga vhdl codegen systemc verilog compiler simulator codegenerator systemverilog
Created 2015-05-19
3,349 commits to master branch, last one 4 months ago
machineware-gmbh
vcml machineware-gmbh
37
151
apache-2.0
11
A modeling library with virtual components for SystemC and TLM simulators
systemc tlm-models
Created 2018-01-22
1,729 commits to main branch, last one 3 days ago
Xilinx
systemctlm-cosim-demo Xilinx
52
143
other
19
QEMU libsystemctlm-soc co-simulation demos.
qemu tlm2 systemc co-simulation
Created 2016-10-27
121 commits to master branch, last one 10 months ago
Minres
SystemC-Components Minres
30
102
apache-2.0
8
A SystemC productivity library: https://minres.github.io/SystemC-Components/
systemc c-plusplus c-plus-plus
Created 2016-10-08
1,702 commits to main branch, last one 24 days ago
anikau31
systemc-clang anikau31
19
82
other
14
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
systemc verilog synthesis plugin-hdl systemc-clang
Created 2013-09-21
2,357 commits to master branch, last one 6 months ago
varunnagpaal
Digital-Hardware-Modelling varunnagpaal
13
65
mit
6
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
hls rtl fpga vhdl vlsi opencl systemc verilog hardware systemverilog digital-systems hardware-models digital-hardware
Created 2016-11-28
104 commits to master branch, last one 2 months ago
Xilinx
pcie-model Xilinx
14
55
other
3
PCI Express controller model
c pcie tlm2 systemc co-simulation
Created 2022-09-21
32 commits to master branch, last one 2 years ago
agra-uni-bremen
crave agra-uni-bremen
13
50
other
13
Constrained random stimuli generation for C++ and SystemC
systemc constrained-random
Created 2012-06-28
1,092 commits to development branch, last one 6 years ago