13 results found Sort:

verilator
verilator verilator
625
2.6k
lgpl-3.0
73
Verilator open-source SystemVerilog simulator and lint system
cpp rtl systemc verilog compilers verilator system-verilog verilog-simulator
Created 2019-06-13
7,537 commits to master branch, last one a day ago
sergeykhbr
riscv_vhdl sergeykhbr
104
633
apache-2.0
53
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
qt cpu soc vhdl riscv systemc debugger simulator
Created 2015-11-08
1,342 commits to master branch, last one about a month ago
accellera-official
systemc accellera-official
155
506
apache-2.0
43
SystemC Reference Implementation
cpp tlm systemc
Created 2019-07-25
4,110 commits to main branch, last one 26 days ago
mariusmm
RISC-V-TLM mariusmm
72
288
gpl-3.0
19
RISC-V SystemC-TLM simulator
tlm2 riscv risc-v systemc
Created 2018-09-10
367 commits to master branch, last one 7 months ago
intel
systemc-compiler intel
38
257
other
17
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
hls llvm clang systemc hardware-designs
Created 2020-10-16
144 commits to main branch, last one 9 days ago
davidepatti
noxim davidepatti
123
250
unknown
18
Network on Chip Simulator
noc noxim systemc simulation university network-analysis
Created 2015-03-23
679 commits to master branch, last one 11 months ago
Xilinx
libsystemctlm-soc Xilinx
69
227
other
21
SystemC/TLM-2.0 Co-simulation framework
qemu tlm2 systemc co-simulation
Created 2016-10-27
588 commits to master branch, last one about a month ago
Nic30
hwt Nic30
27
204
mit
18
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
hcl hls rtl uvm fpga vhdl codegen systemc verilog compiler simulator codegenerator systemverilog
Created 2015-05-19
3,349 commits to master branch, last one 28 days ago
machineware-gmbh
vcml machineware-gmbh
35
136
apache-2.0
11
A modeling library with virtual components for SystemC and TLM simulators
systemc tlm-models
Created 2018-01-22
1,657 commits to main branch, last one 2 days ago
Xilinx
systemctlm-cosim-demo Xilinx
47
132
other
20
QEMU libsystemctlm-soc co-simulation demos.
qemu tlm2 systemc co-simulation
Created 2016-10-27
121 commits to master branch, last one 6 months ago
Minres
SystemC-Components Minres
27
100
apache-2.0
9
A SystemC productivity library: https://minres.github.io/SystemC-Components/
systemc c-plusplus c-plus-plus
Created 2016-10-08
1,596 commits to main branch, last one 4 months ago
anikau31
systemc-clang anikau31
19
79
other
14
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
systemc verilog synthesis plugin-hdl systemc-clang
Created 2013-09-21
2,357 commits to master branch, last one 2 months ago
Xilinx
pcie-model Xilinx
12
46
other
4
PCI Express controller model
c pcie tlm2 systemc co-simulation
Created 2022-09-21
32 commits to master branch, last one 2 years ago