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varunnagpaal
Digital-Hardware-Modelling varunnagpaal
13
64
mit
6
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
hls rtl fpga vhdl vlsi opencl systemc verilog hardware systemverilog digital-systems hardware-models digital-hardware
Created 2016-11-28
104 commits to master branch, last one about a month ago