21 results found Sort:

The-OpenROAD-Project
OpenLane The-OpenROAD-Project
373
1.4k
apache-2.0
59
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip
Created 2020-07-20
1,892 commits to master branch, last one about a month ago
limbo018
DREAMPlace limbo018
202
700
bsd-3-clause
21
Deep learning toolkit-enabled VLSI placement
vlsi pytorch deep-learning vlsi-placement gpu-acceleration vlsi-physical-design
Created 2019-02-28
761 commits to master branch, last one 9 days ago
OpenTimer
OpenTimer OpenTimer
145
564
other
47
A High-performance Timing Analysis Tool for VLSI Systems
cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2015-07-14
216 commits to master branch, last one about a year ago
DegateCommunity
Degate DegateCommunity
31
251
gpl-3.0
16
A modern and open-source cross-platform software for chips reverse engineering.
cpp gui vhdl vlsi chips verilog security cybersecurity cross-platform multi-platform security-tools reverse-engineering
Created 2020-07-16
1,168 commits to develop branch, last one 2 months ago
efabless
openlane2 efabless
38
206
apache-2.0
12
The next generation of OpenLane, rewritten from scratch with a modular architecture
drc eda lvs pdk pnr sta asic flow vlsi flows gdsii sky130 silicon verilog gf180mcu openlane openroad rtl-to-gds
Created 2023-01-16
396 commits to main branch, last one 8 days ago
arm-university
VLSI-Fundamentals-Education-Kit arm-university
51
205
unknown
6
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical impl...
arm vlsi synopsys-design cadence-virtuoso hardware-designs computer-engineering electrical-engineering devices-circuits-materials microprocessor-implementation
Created 2021-11-25
33 commits to main branch, last one 3 months ago
AUCOHL
DFFRAM AUCOHL
32
133
apache-2.0
14
Standard Cell Library based Memory Compiler using FF/Latch cells
vlsi verilog asic-design vlsi-circuits electronics-design vlsi-physical-design
Created 2020-11-09
281 commits to main branch, last one 10 months ago
phoeniX-Digital-Design
phoeniX phoeniX-Digital-Design
81
118
gpl-3.0
5
RISC-V Embedded Processor for Approximate Computing
cpu fpga vlsi riscv risc-v cpu-design microprocessor embedded-systems approximate-computing computer-architecture
Created 2023-08-12
1,532 commits to main branch, last one 4 days ago
purdue-onchip
gds2Para purdue-onchip
19
114
gpl-2.0
10
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation
Created 2018-10-05
233 commits to master branch, last one about a year ago
antonblanchard
vlsiffra antonblanchard
9
109
apache-2.0
8
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
vlsi adder booth dadda verilog multiplier amaranth-hdl physical-design
Created 2022-05-29
30 commits to main branch, last one about a year ago
eelab-dev
EEcircuit eelab-dev
7
105
mit
8
A browser-based SPICE circuit simulator
cmos vlsi wasm spice circuit ngspice emscripten simulation webgl-plot electronics webassembly
Created 2020-10-12
293 commits to main branch, last one about a month ago
asyncvlsi
act asyncvlsi
22
99
gpl-2.0
16
ACT hardware description language and core tools.
cad chp eda hdl prs vlsi dataflow language vlsi-cad production-rules asynchronous-vlsi circuit-simulator design-automation dataflow-programming asynchronous-circuits hardware-description-language communicating-hardware-processes
Created 2018-12-10
1,945 commits to master branch, last one 7 days ago
cuhk-eda
Xplace cuhk-eda
8
97
bsd-3-clause
7
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
eda gpu vlsi placement physical-design gpu-acceleration routability-driven
Created 2022-10-20
55 commits to main branch, last one 4 months ago
viktor-prutyanov
drec-fpga-intro viktor-prutyanov
28
92
mit
10
Материалы для курсов "Введение в проектирование на языке Verilog" (2024+), "Введение в FPGA и Verilog" (2018-2019)
asic fpga vlsi risc-v verilog education
Created 2019-01-30
61 commits to master branch, last one 2 days ago
NTU-LaDS-II
FAN_ATPG NTU-LaDS-II
9
77
mit
2
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
cli cpp eda lex atpg vlsi yacc fan-out verilog stuck-at test-pattern vlsi-testing fault-simulation sequential-circuits combinational-circuits electronic-design-automation
Created 2022-10-02
130 commits to main branch, last one 11 months ago
hsluoyz
Atalanta hsluoyz
34
75
unknown
8
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
atpg vlsi verilog atalanta
Created 2013-04-30
2 commits to master branch, last one 6 months ago
ahmed-agiza
EDAViewer ahmed-agiza
12
68
mit
3
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
cgo def eda lef vlsi webgl layout opendb pixijs viewer hardware def-viewer serverless digitaldesign hardware-design opendb-database physical-synthesis server-side-rendering serverless-side-rendering electronic-design-automation
Created 2020-07-16
1 commits to master branch, last one 4 years ago
OpenTimer
Parser-SPEF OpenTimer
20
51
mit
8
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2018-08-08
215 commits to master branch, last one 2 years ago
AngeloJacobo
OpenLANE-Sky130-Physical-Design-Workshop AngeloJacobo
15
48
mit
2
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic vlsi sky130 rtl2gds openlane openlane-flow vlsi-physical-design
Created 2022-08-04
150 commits to main branch, last one 2 years ago
twweeb
VLSI-Physical-Design-Automation twweeb
8
41
unknown
2
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
eda nthu vlsi vlsi-cad vlsi-design vlsi-routing fixed-outline global-routing vlsi-floorplan vlsi-placement two-way-min-cut global-placement vlsi-physical-design physical-design-automation
Created 2020-11-05
29 commits to master branch, last one 3 years ago
Akashtailor-exe
30-days-of-verilog Akashtailor-exe
4
29
unknown
1
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
vlsi verilog rtl-coding rtl-design 30daysofcode digitalcircuit 30-days-of-code verilog-project verilog-programs digital-logic-design
Created 2023-08-30
48 commits to main branch, last one about a year ago