25 results found Sort:

The-OpenROAD-Project
OpenLane The-OpenROAD-Project
394
1.5k
apache-2.0
62
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip
Created 2020-07-20
1,893 commits to master branch, last one 3 months ago
limbo018
DREAMPlace limbo018
216
770
bsd-3-clause
22
Deep learning toolkit-enabled VLSI placement
vlsi pytorch deep-learning vlsi-placement gpu-acceleration vlsi-physical-design
Created 2019-02-28
771 commits to master branch, last one 2 months ago
OpenTimer
OpenTimer OpenTimer
153
603
other
48
A High-performance Timing Analysis Tool for VLSI Systems
cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2015-07-14
216 commits to master branch, last one 2 years ago
efabless
openlane2 efabless
59
276
apache-2.0
13
The next generation of OpenLane, rewritten from scratch with a modular architecture
drc eda lvs pdk pnr sta asic flow vlsi flows gdsii sky130 silicon verilog gf180mcu openlane openroad rtl-to-gds
Created 2023-01-16
417 commits to main branch, last one about a month ago
DegateCommunity
Degate DegateCommunity
33
259
gpl-3.0
15
A modern and open-source cross-platform software for chips reverse engineering.
cpp gui vhdl vlsi chips verilog security cybersecurity cross-platform multi-platform security-tools reverse-engineering
Created 2020-07-16
1,195 commits to develop branch, last one 4 months ago
arm-university
VLSI-Fundamentals-Education-Kit arm-university
56
235
unknown
6
Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical impl...
arm vlsi synopsys-design cadence-virtuoso hardware-designs computer-engineering electrical-engineering devices-circuits-materials microprocessor-implementation
Created 2021-11-25
33 commits to main branch, last one 8 months ago
AUCOHL
DFFRAM AUCOHL
34
144
apache-2.0
13
Standard Cell Library based Memory Compiler using FF/Latch cells
vlsi verilog asic-design vlsi-circuits electronics-design vlsi-physical-design
Created 2020-11-09
281 commits to main branch, last one about a year ago
phoeniX-Digital-Design
phoeniX phoeniX-Digital-Design
82
124
gpl-3.0
5
RISC-V Embedded Processor for Approximate Computing
cpu fpga vlsi riscv risc-v cpu-design microprocessor embedded-systems approximate-computing computer-architecture
Created 2023-08-12
1,536 commits to main branch, last one 3 days ago
cuhk-eda
Xplace cuhk-eda
14
119
bsd-3-clause
8
Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization
eda gpu vlsi placement physical-design gpu-acceleration routability-driven
Created 2022-10-20
59 commits to main branch, last one 3 months ago
purdue-onchip
gds2Para purdue-onchip
23
117
gpl-2.0
9
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation
Created 2018-10-05
233 commits to master branch, last one about a year ago
eelab-dev
EEcircuit eelab-dev
10
116
mit
8
A browser-based SPICE circuit simulator
cmos vlsi wasm spice circuit ngspice emscripten simulation webgl-plot electronics webassembly
Created 2020-10-12
362 commits to main branch, last one 9 days ago
antonblanchard
vlsiffra antonblanchard
9
111
apache-2.0
7
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
vlsi adder booth dadda verilog multiplier amaranth-hdl physical-design
Created 2022-05-29
30 commits to main branch, last one about a year ago
asyncvlsi
act asyncvlsi
26
107
gpl-2.0
15
ACT hardware description language and core tools.
cad chp eda hdl prs vlsi dataflow language vlsi-cad production-rules asynchronous-vlsi circuit-simulator design-automation dataflow-programming asynchronous-circuits hardware-description-language communicating-hardware-processes
Created 2018-12-10
2,021 commits to master branch, last one 16 days ago
viktor-prutyanov
drec-fpga-intro viktor-prutyanov
32
96
mit
9
Материалы для курсов по проектированию цифровых вычислительных систем
asic fpga vlsi risc-v verilog education
Created 2019-01-30
132 commits to master branch, last one 11 days ago
NTU-LaDS-II
FAN_ATPG NTU-LaDS-II
11
86
mit
2
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
cli cpp eda lex atpg vlsi yacc fan-out verilog stuck-at test-pattern vlsi-testing fault-simulation sequential-circuits combinational-circuits electronic-design-automation
Created 2022-10-02
130 commits to main branch, last one about a year ago
hsluoyz
Atalanta hsluoyz
35
78
unknown
8
Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.
atpg vlsi verilog atalanta
Created 2013-04-30
2 commits to master branch, last one 11 months ago
ahmed-agiza
EDAViewer ahmed-agiza
12
70
mit
3
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
cgo def eda lef vlsi webgl layout opendb pixijs viewer hardware def-viewer serverless digitaldesign hardware-design opendb-database physical-synthesis server-side-rendering serverless-side-rendering electronic-design-automation
Created 2020-07-16
1 commits to master branch, last one 4 years ago
varunnagpaal
Digital-Hardware-Modelling varunnagpaal
13
64
mit
6
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
hls rtl fpga vhdl vlsi opencl systemc verilog hardware systemverilog digital-systems hardware-models digital-hardware
Created 2016-11-28
104 commits to master branch, last one about a month ago
AngeloJacobo
OpenLANE-Sky130-Physical-Design-Workshop AngeloJacobo
15
56
mit
2
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic vlsi sky130 rtl2gds openlane openlane-flow vlsi-physical-design
Created 2022-08-04
150 commits to main branch, last one 2 years ago
OpenTimer
Parser-SPEF OpenTimer
24
55
mit
7
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2018-08-08
215 commits to master branch, last one 2 years ago
twweeb
VLSI-Physical-Design-Automation twweeb
8
41
unknown
2
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
eda nthu vlsi vlsi-cad vlsi-design vlsi-routing fixed-outline global-routing vlsi-floorplan vlsi-placement two-way-min-cut global-placement vlsi-physical-design physical-design-automation
Created 2020-11-05
29 commits to master branch, last one 4 years ago
briansune
Delta-Sigma-DAC-Verilog briansune
6
37
mit
1
Delta Sigma DAC FPGA
dac fpga vlsi verilog delta-sigma
Created 2022-04-22
18 commits to main branch, last one about a month ago
imsanjoykb
Electrical-And-Electronic-Engineering-Course-Materials imsanjoykb
3
35
apache-2.0
2
Electrical And Electronic Engineering Course Materials
vlsi handnote eee-ourse fabrication vlsi-course power-system vlsi-circuits course-materials solid-state-device eee-semester-course circute-design-course biomedical-engineering electrical-engineering electronics-engineering power-syetem-protection control-systems-engineering
Created 2021-01-12
124 commits to main branch, last one 3 years ago
tharunchitipolu
Dadda-Multiplier-using-CSA tharunchitipolu
7
33
mpl-2.0
1
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
rtl vlsi verilog wallace fulladder dadda-tree multiplier vlsi-design vlsi-project carry-save-adder dadda-multiplier tree-multipliers fast-multiplication hardware-description-language
Created 2021-04-19
10 commits to main branch, last one 10 months ago
Akashtailor-exe
30-days-of-verilog Akashtailor-exe
4
32
unknown
1
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
vlsi verilog rtl-coding rtl-design 30daysofcode digitalcircuit 30-days-of-code verilog-project verilog-programs digital-logic-design
Created 2023-08-30
48 commits to main branch, last one about a year ago