Search Results - RepositoryStats

379

1.4k

apache-2.0

61

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

rtl asic vlsi 130nm magic yosys netgen caravel foundry klayout openram rtl2gds verilog openroad skywater soc-design system-on-chip

Created 2020-07-20

1,892 commits to master branch, last one 2 months ago

DREAMPlace limbo018

208

726

bsd-3-clause

22

Deep learning toolkit-enabled VLSI placement

vlsi pytorch deep-learning vlsi-placement gpu-acceleration vlsi-physical-design

Created 2019-02-28

761 commits to master branch, last one about a month ago

OpenTimer OpenTimer

144

577

other

48

A High-performance Timing Analysis Tool for VLSI Systems

cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Created 2015-07-14

216 commits to master branch, last one 2 years ago

Degate DegateCommunity

33

255

gpl-3.0

16

A modern and open-source cross-platform software for chips reverse engineering.

cpp gui vhdl vlsi chips verilog security cybersecurity cross-platform multi-platform security-tools reverse-engineering

Created 2020-07-16

1,195 commits to develop branch, last one 26 days ago

openlane2 efabless

41

246

apache-2.0

13

The next generation of OpenLane, rewritten from scratch with a modular architecture

drc eda lvs pdk pnr sta asic flow vlsi flows gdsii sky130 silicon verilog gf180mcu openlane openroad rtl-to-gds

Created 2023-01-16

406 commits to main branch, last one 3 days ago

VLSI-Fundamentals-Education-Kit arm-university

54

217

unknown

6

Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied in the design of simple logic circuits and in the physical impl...

arm vlsi synopsys-design cadence-virtuoso hardware-designs computer-engineering electrical-engineering devices-circuits-materials microprocessor-implementation

Created 2021-11-25

33 commits to main branch, last one 4 months ago

DFFRAM AUCOHL

33

137

apache-2.0

14

Standard Cell Library based Memory Compiler using FF/Latch cells

vlsi verilog asic-design vlsi-circuits electronics-design vlsi-physical-design

Created 2020-11-09

281 commits to main branch, last one 11 months ago

phoeniX phoeniX-Digital-Design

80

120

gpl-3.0

5

RISC-V Embedded Processor for Approximate Computing

cpu fpga vlsi riscv risc-v cpu-design microprocessor embedded-systems approximate-computing computer-architecture

Created 2023-08-12

1,532 commits to main branch, last one about a month ago

gds2Para purdue-onchip

19

117

gpl-2.0

10

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation

Created 2018-10-05

233 commits to master branch, last one about a year ago

vlsiffra antonblanchard

9

110

apache-2.0

8

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

vlsi adder booth dadda verilog multiplier amaranth-hdl physical-design

Created 2022-05-29

30 commits to main branch, last one about a year ago

EEcircuit eelab-dev

8

109

mit

8

A browser-based SPICE circuit simulator

cmos vlsi wasm spice circuit ngspice emscripten simulation webgl-plot electronics webassembly

Created 2020-10-12

313 commits to main branch, last one 5 days ago

Xplace cuhk-eda

9

105

bsd-3-clause

8

Xplace 2.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability Optimization

eda gpu vlsi placement physical-design gpu-acceleration routability-driven

Created 2022-10-20

59 commits to main branch, last one 4 days ago

act asyncvlsi

25

104

gpl-2.0

16

ACT hardware description language and core tools.

cad chp eda hdl prs vlsi dataflow language vlsi-cad production-rules asynchronous-vlsi circuit-simulator design-automation dataflow-programming asynchronous-circuits hardware-description-language communicating-hardware-processes

Created 2018-12-10

1,976 commits to master branch, last one 8 hours ago

drec-fpga-intro viktor-prutyanov

28

93

mit

10

Материалы для курсов "Введение в проектирование на языке Verilog" (2024+), "Введение в FPGA и Verilog" (2018-2019)

asic fpga vlsi risc-v verilog education

Created 2019-01-30

61 commits to master branch, last one about a month ago

FAN_ATPG NTU-LaDS-II

11

78

mit

2

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

cli cpp eda lex atpg vlsi yacc fan-out verilog stuck-at test-pattern vlsi-testing fault-simulation sequential-circuits combinational-circuits electronic-design-automation

Created 2022-10-02

130 commits to main branch, last one about a year ago

Atalanta hsluoyz

34

76

unknown

8

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

atpg vlsi verilog atalanta

Created 2013-04-30

2 commits to master branch, last one 7 months ago

EDAViewer ahmed-agiza

12

69

mit

3

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Created 2020-07-16

1 commits to master branch, last one 4 years ago

Parser-SPEF OpenTimer

21

53

mit

8

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Created 2018-08-08

215 commits to master branch, last one 2 years ago

OpenLANE-Sky130-Physical-Design-Workshop AngeloJacobo

15

51

mit

2

Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

asic vlsi sky130 rtl2gds openlane openlane-flow vlsi-physical-design

Created 2022-08-04

150 commits to main branch, last one 2 years ago

VLSI-Physical-Design-Automation twweeb

8

41

unknown

2

Courseworks of CS6165 VLSI Physical Design Automation, NTHU.

eda nthu vlsi vlsi-cad vlsi-design vlsi-routing fixed-outline global-routing vlsi-floorplan vlsi-placement two-way-min-cut global-placement vlsi-physical-design physical-design-automation

Created 2020-11-05

29 commits to master branch, last one 3 years ago

Dadda-Multiplier-using-CSA tharunchitipolu

6

36

mpl-2.0

2

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.

rtl vlsi verilog wallace fulladder dadda-tree multiplier vlsi-design vlsi-project carry-save-adder dadda-multiplier tree-multipliers fast-multiplication hardware-description-language

Created 2021-04-19

10 commits to main branch, last one 6 months ago

Electrical-And-Electronic-Engineering-Course-Materials imsanjoykb

2

35

apache-2.0

3

Electrical And Electronic Engineering Course Materials

vlsi handnote eee-ourse fabrication vlsi-course power-system vlsi-circuits course-materials solid-state-device eee-semester-course circute-design-course biomedical-engineering electrical-engineering electronics-engineering power-syetem-protection control-systems-engineering

Created 2021-01-12

124 commits to main branch, last one 2 years ago

Delta-Sigma-DAC-Verilog briansune

5

32

mit

2

Delta Sigma DAC FPGA

dac fpga vlsi verilog delta-sigma

Created 2022-04-22

17 commits to main branch, last one 11 months ago

30-days-of-verilog Akashtailor-exe

4

29

unknown

1

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

vlsi verilog rtl-coding rtl-design 30daysofcode digitalcircuit 30-days-of-code verilog-project verilog-programs digital-logic-design

Created 2023-08-30

48 commits to main branch, last one about a year ago