6 results found Sort:

OpenTimer
OpenTimer OpenTimer
145
573
other
48
A High-performance Timing Analysis Tool for VLSI Systems
cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2015-07-14
216 commits to master branch, last one 2 years ago
efabless
openlane2 efabless
39
220
apache-2.0
12
The next generation of OpenLane, rewritten from scratch with a modular architecture
drc eda lvs pdk pnr sta asic flow vlsi flows gdsii sky130 silicon verilog gf180mcu openlane openroad rtl-to-gds
Created 2023-01-16
401 commits to main branch, last one 8 days ago
verilog-to-routing
tatum verilog-to-routing
10
55
mit
9
Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits
cad eda sta tatum
Created 2015-09-01
846 commits to master branch, last one 4 years ago
michael-dev
ebtables-dhcpsnooping michael-dev
15
52
gpl-3.0
6
Linux generic dhcp snooping daemon using nflog and ebtables or nftables
c sta lease dhcp-server dhcp-request ebtables-rules
Created 2013-03-27
183 commits to master branch, last one 2 years ago
OpenTimer
Parser-SPEF OpenTimer
21
52
mit
8
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2018-08-08
215 commits to master branch, last one 2 years ago
vlsiexcellence
Static-Timing-Analysis-Full-Course vlsiexcellence
10
43
unknown
1
Static Timing Analysis Full Course
sta
Created 2023-01-13
17 commits to main branch, last one about a year ago