OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Date Created 2015-07-14 (8 years ago)

Commits 216 (last one about a year ago)

Stargazers 528 (3 this week)

Watchers 47 (0 this week)

Forks 145

License other

Ranking

RepositoryStats indexes 533,807 repositories, of these OpenTimer/OpenTimer is ranked #82,332 (85th percentile) for total stargazers, and #44,024 for total watchers. Github reports the primary language for this repository as Verilog, for repositories using this language it is ranked #38/456.

OpenTimer/OpenTimer is also tagged with popular topics, for these it's ranked: verilog (#45/257), cad (#40/168), eda (#28/126)

Other Information

OpenTimer/OpenTimer has 4 open pull requests on Github, 5 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 51 open issues and 19 closed issues.

All Topics

cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Star History

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

7 commits on the default branch (master) since jan '22

Yearly Commits

Commits to the default branch (master) per year

Issue History

Languages

The primary language is Verilog but there's also others...

updated: 2024-06-26 @ 11:18am, id: 39079545 / R_kgDOAlROeQ