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145
570
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48
A High-performance Timing Analysis Tool for VLSI Systems
Created 2015-07-14
216 commits to master branch, last one 2 years ago
81
447
mit
9
A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)
Created 2023-02-23
1,521 commits to main branch, last one 4 days ago
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
Created 2022-12-26
262 commits to main branch, last one 13 days ago
19
114
gpl-2.0
10
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Created 2018-10-05
233 commits to master branch, last one about a year ago
22
92
bsd-3-clause
14
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
Created 2019-09-23
875 commits to master branch, last one about a year ago
A Standalone Structural Verilog Parser
Created 2019-01-04
67 commits to master branch, last one 3 years ago
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
Created 2022-10-02
130 commits to main branch, last one about a year ago
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
Created 2020-07-16
1 commits to master branch, last one 4 years ago
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Created 2018-08-08
215 commits to master branch, last one 2 years ago