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145

564

other

47

A High-performance Timing Analysis Tool for VLSI Systems

cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Created 2015-07-14

216 commits to master branch, last one about a year ago

rl4co ai4co

80

432

mit

8

A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)

tsp cvrp hydra torchrl attention benchmark scheduling tensordict attention-model pytorch-lightning operations-research reinforcement-learning vehicle-routing-problem combinatorial-optimization electronic-design-automation neural-combinatorial-optimization

Created 2023-02-23

1,518 commits to main branch, last one 9 days ago

CHARM arc-research-lab

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123

mit

7

CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture

acap fpga versal versalacap deeplearning high-level-synthesis heterogeneous-computing design-space-exploration domain-specific-architecture electronic-design-automation

Created 2022-12-26

259 commits to main branch, last one 2 months ago

reevo ai4co

26

120

mit

4

[NeurIPS 2024] ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution

llm-agent hyper-heuristics genetic-algorithm bin-packing-problem orienteering-problem large-language-models reinforcement-learning ant-colony-optimization evolutionary-algorithms vehicle-routing-problem multiple-knapsack-problem traveling-salesman-problem electronic-design-automation automatic-algorithm-generation neural-combinatorial-optimization

Created 2023-11-20

282 commits to main branch, last one 3 days ago

gds2Para purdue-onchip

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114

gpl-2.0

10

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation

Created 2018-10-05

233 commits to master branch, last one about a year ago

spydrnet byuccl

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91

bsd-3-clause

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A flexible framework for analyzing and transforming FPGA netlists. Official repository.

cad eda edif fpga fpgas circuit digital netlist circuits hardware netlists circuit-design netlist-parser transformation transformations circuit-analysis hardware-designs computer-aided-design electronic-design-automation

Created 2019-09-23

875 commits to master branch, last one about a year ago

Parser-Verilog OpenTimer

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83

mit

8

A Standalone Structural Verilog Parser

eda flex cpp17 circuit verilog bison-yacc vlsi-circuits vlsi-physical-design computer-aided-design electronic-design-automation

Created 2019-01-04

67 commits to master branch, last one 3 years ago

FAN_ATPG NTU-LaDS-II

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77

mit

2

FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool

cli cpp eda lex atpg vlsi yacc fan-out verilog stuck-at test-pattern vlsi-testing fault-simulation sequential-circuits combinational-circuits electronic-design-automation

Created 2022-10-02

130 commits to main branch, last one 11 months ago

EDAViewer ahmed-agiza

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mit

3

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Created 2020-07-16

1 commits to master branch, last one 4 years ago

Parser-SPEF OpenTimer

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51

mit

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A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation

Created 2018-08-08

215 commits to master branch, last one 2 years ago