10 results found Sort:

OpenTimer
OpenTimer OpenTimer
142
551
other
47
A High-performance Timing Analysis Tool for VLSI Systems
cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2015-07-14
216 commits to master branch, last one about a year ago
ai4co
rl4co ai4co
72
399
mit
7
A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)
tsp cvrp hydra torchrl attention benchmark scheduling tensordict attention-model pytorch-lightning operations-research reinforcement-learning vehicle-routing-problem combinatorial-optimization electronic-design-automation neural-combinatorial-optimization
Created 2023-02-23
1,495 commits to main branch, last one 9 days ago
arc-research-lab
CHARM arc-research-lab
18
119
mit
6
CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture
acap fpga versal versalacap deeplearning high-level-synthesis heterogeneous-computing design-space-exploration domain-specific-architecture electronic-design-automation
Created 2022-12-26
259 commits to main branch, last one about a month ago
purdue-onchip
gds2Para purdue-onchip
18
111
gpl-2.0
10
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation
Created 2018-10-05
233 commits to master branch, last one about a year ago
ai4co
LLM-as-HH ai4co
21
95
mit
4
[NeurIPS 2024] Large Language Models as Hyper-Heuristics for Combinatorial Optimization (CO)
llm-agent hyper-heuristics genetic-algorithm bin-packing-problem orienteering-problem large-language-models reinforcement-learning ant-colony-optimization evolutionary-algorithms vehicle-routing-problem multiple-knapsack-problem traveling-salesman-problem electronic-design-automation automatic-algorithm-generation neural-combinatorial-optimization
Created 2023-11-20
261 commits to main branch, last one 2 days ago
byuccl
spydrnet byuccl
21
89
bsd-3-clause
14
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad eda edif fpga fpgas circuit digital netlist circuits hardware netlists circuit-design netlist-parser transformation transformations circuit-analysis hardware-designs computer-aided-design electronic-design-automation
Created 2019-09-23
875 commits to master branch, last one about a year ago
OpenTimer
Parser-Verilog OpenTimer
33
79
mit
8
A Standalone Structural Verilog Parser
eda flex cpp17 circuit verilog bison-yacc vlsi-circuits vlsi-physical-design computer-aided-design electronic-design-automation
Created 2019-01-04
67 commits to master branch, last one 3 years ago
NTU-LaDS-II
FAN_ATPG NTU-LaDS-II
9
76
mit
2
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
cli cpp eda lex atpg vlsi yacc fan-out verilog stuck-at test-pattern vlsi-testing fault-simulation sequential-circuits combinational-circuits electronic-design-automation
Created 2022-10-02
130 commits to main branch, last one 10 months ago
ahmed-agiza
EDAViewer ahmed-agiza
12
67
mit
3
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
cgo def eda lef vlsi webgl layout opendb pixijs viewer hardware def-viewer serverless digitaldesign hardware-design opendb-database physical-synthesis server-side-rendering serverless-side-rendering electronic-design-automation
Created 2020-07-16
1 commits to master branch, last one 4 years ago
OpenTimer
Parser-SPEF OpenTimer
19
50
mit
7
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2018-08-08
215 commits to master branch, last one 2 years ago