15 results found Sort:

OpenTimer
OpenTimer OpenTimer
153
606
other
48
A High-performance Timing Analysis Tool for VLSI Systems
cad eda sta vlsi cpp17 verilog vlsi-circuits circuit-analysis circuit-simulator circuit-simulation parallel-computing vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2015-07-14
216 commits to master branch, last one 2 years ago
ai4co
rl4co ai4co
97
551
mit
8
A PyTorch library for all things Reinforcement Learning (RL) for Combinatorial Optimization (CO)
tsp cvrp hydra torchrl attention benchmark scheduling tensordict attention-model pytorch-lightning operations-research reinforcement-learning vehicle-routing-problem combinatorial-optimization electronic-design-automation neural-combinatorial-optimization
Created 2023-02-23
1,590 commits to main branch, last one 4 days ago
ai4co
reevo ai4co
35
170
mit
4
[NeurIPS 2024] ReEvo: Large Language Models as Hyper-Heuristics with Reflective Evolution
llm-agent hyper-heuristics genetic-algorithm bin-packing-problem orienteering-problem large-language-models reinforcement-learning ant-colony-optimization evolutionary-algorithms vehicle-routing-problem multiple-knapsack-problem traveling-salesman-problem electronic-design-automation automatic-algorithm-generation neural-combinatorial-optimization
Created 2023-11-20
297 commits to main branch, last one 8 days ago
arc-research-lab
CHARM arc-research-lab
22
137
mit
7
CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
acap fpga versal versalacap deeplearning high-level-synthesis heterogeneous-computing design-space-exploration domain-specific-architecture electronic-design-automation
Created 2022-12-26
306 commits to main branch, last one a day ago
purdue-onchip
gds2Para purdue-onchip
23
118
gpl-2.0
9
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
eda spef vlsi gdsii parse interconnect vlsi-circuits integrated-circuits electronic-design-automation
Created 2018-10-05
233 commits to master branch, last one about a year ago
byuccl
spydrnet byuccl
23
96
bsd-3-clause
13
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad eda edif fpga fpgas circuit digital netlist circuits hardware netlists circuit-design netlist-parser transformation transformations circuit-analysis hardware-designs computer-aided-design electronic-design-automation
Created 2019-09-23
875 commits to master branch, last one about a year ago
OpenTimer
Parser-Verilog OpenTimer
36
90
mit
7
A Standalone Structural Verilog Parser
eda flex cpp17 circuit verilog bison-yacc vlsi-circuits vlsi-physical-design computer-aided-design electronic-design-automation
Created 2019-01-04
67 commits to master branch, last one 3 years ago
NTU-LaDS-II
FAN_ATPG NTU-LaDS-II
11
86
mit
2
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
cli cpp eda lex atpg vlsi yacc fan-out verilog stuck-at test-pattern vlsi-testing fault-simulation sequential-circuits combinational-circuits electronic-design-automation
Created 2022-10-02
130 commits to main branch, last one about a year ago
ahmed-agiza
EDAViewer ahmed-agiza
12
70
mit
3
EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
cgo def eda lef vlsi webgl layout opendb pixijs viewer hardware def-viewer serverless digitaldesign hardware-design opendb-database physical-synthesis server-side-rendering serverless-side-rendering electronic-design-automation
Created 2020-07-16
1 commits to master branch, last one 4 years ago
OpenTimer
Parser-SPEF OpenTimer
24
55
mit
7
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
eda sta spef vlsi cpp17 circuits parasitic vlsi-circuits vlsi-physical-design computer-aided-design static-timing-analysis electronic-design-automation
Created 2018-08-08
215 commits to master branch, last one 2 years ago
PrimisAI
nexus PrimisAI
3
48
mit
3
A powerful Python framework for orchestrating AI agents and managing complex LLM-driven tasks with ease.
agents reasoning-agent agentic-framework multi-agent-systems large-language-models electronic-design-automation
Created 2024-11-19
47 commits to main branch, last one 27 days ago
najaeda
naja-verilog najaeda
2
35
apache-2.0
3
A standalone structural (gate-level) verilog parser
cpp eda parser netlist verilog semiconductor netlist-parser electronic-design-automation
Created 2022-10-11
133 commits to main branch, last one 4 months ago
LukeVassallo
RL_PCB LukeVassallo
10
33
mit
1
RL_PCB is a novel learning-based method for optimising the placement of circuit components on a Printed Circuit Board (PCB).
placement pcb-design pcb-layout optimization machine-learning reinforcement-learning artificial-intelligence electronic-design-automation
Created 2023-04-26
126 commits to main branch, last one 10 months ago
ycchen218
EDA-IRdrop-Prediction ycchen218
4
27
unknown
2
This is a deep-learning based model for Electronic Design Automation(EDA), predicting the IR drop location on the chip.
eda python ir-drop pytorch deep-learning machine-learning prediction-model electronic-design-automation
Created 2023-06-07
14 commits to master branch, last one about a year ago
cornell-zhang
HOGA cornell-zhang
4
26
bsd-3-clause
7
Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
graph-learning logic-synthesis graph-transformer distributed-training electronic-design-automation
Created 2024-03-06
17 commits to master branch, last one 7 months ago