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spydrnet byuccl
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bsd-3-clause
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A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad eda edif fpga fpgas circuit digital netlist circuits hardware netlists circuit-design netlist-parser transformation transformations circuit-analysis hardware-designs computer-aided-design electronic-design-automation
Created 2019-09-23
875 commits to master branch, last one about a year ago