2 results found Sort:

byuccl
spydrnet byuccl
22
92
bsd-3-clause
14
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad eda edif fpga fpgas circuit digital netlist circuits hardware netlists circuit-design netlist-parser transformation transformations circuit-analysis hardware-designs computer-aided-design electronic-design-automation
Created 2019-09-23
875 commits to master branch, last one about a year ago
najaeda
naja-verilog najaeda
2
33
apache-2.0
3
A standalone structural (gate-level) verilog parser
cpp eda parser netlist verilog semiconductor netlist-parser electronic-design-automation
Created 2022-10-11
133 commits to main branch, last one about a month ago