byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.

Date Created 2019-09-23 (5 years ago)

Commits 875 (last one about a year ago)

Stargazers 92 (0 this week)

Watchers 14 (0 this week)

Forks 22

License bsd-3-clause

Ranking

RepositoryStats indexes 610,149 repositories, of these byuccl/spydrnet is ranked #316,585 (48th percentile) for total stargazers, and #156,676 for total watchers. Github reports the primary language for this repository as Python, for repositories using this language it is ranked #59,509/123,095.

byuccl/spydrnet is also tagged with popular topics, for these it's ranked: fpga (#277/498), hardware (#265/464), cad (#124/190), eda (#92/144)

Other Information

byuccl/spydrnet has 1 open pull request on Github, 89 pull requests have been merged over the lifetime of the repository.

Github issues are enabled, there are 43 open issues and 82 closed issues.

There have been 21 releases, the latest one was published on 2023-09-14 (about a year ago) with the name SpyDrNet 1.13.0.

Homepage URL: https://byuccl.github.io/spydrnet

All Topics

cad eda edif fpga fpgas circuit digital netlist circuits hardware netlists circuit-design netlist-parser transformation transformations circuit-analysis hardware-designs computer-aided-design electronic-design-automation

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Watcher History

Github watchers over time, collection started in '23

Recent Commit History

207 commits on the default branch (master) since jan '22

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Languages

The primary language is Python but there's also others...

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updated: 2024-11-14 @ 09:46am, id: 210388987 / R_kgDODIpH-w