6 results found Sort:

nturley
netlistsvg nturley
84
650
mit
26
draws an SVG schematic from a JSON netlist
elk yosys klayjs diagram netlist visualization
Created 2016-11-30
245 commits to master branch, last one 11 months ago
emsec
hal emsec
76
632
mit
26
HAL – The Hardware Analyzer
hal fpga netlist hardware security embedded-security integrated-circuits reverse-engineering
Created 2019-02-04
5,331 commits to master branch, last one about a month ago
circuitgraph
circuitgraph circuitgraph
14
110
mit
3
Tools for working with circuits as graphs in python
eda graphs python netlist satisfiability boolean-circuits
Created 2020-07-12
253 commits to main branch, last one about a year ago
byuccl
spydrnet byuccl
22
92
bsd-3-clause
14
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
cad eda edif fpga fpgas circuit digital netlist circuits hardware netlists circuit-design netlist-parser transformation transformations circuit-analysis hardware-designs computer-aided-design electronic-design-automation
Created 2019-09-23
875 commits to master branch, last one about a year ago
najaeda
naja najaeda
12
73
apache-2.0
9
Structural Netlist API (and more) for EDA post synthesis flow development
cpp eda asic fpga netlist verilog semiconductor
Created 2021-10-08
1,110 commits to main branch, last one 4 days ago
najaeda
naja-verilog najaeda
1
30
apache-2.0
3
A standalone structural (gate-level) verilog parser
cpp eda parser netlist verilog semiconductor netlist-parser electronic-design-automation
Created 2022-10-11
133 commits to main branch, last one 25 days ago